ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 367

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.12 Automatic Wait States
25.12.1
Figure 25-13. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Chip Select Wait States
NBS0, NBS1,
D[15:0]
A[23:2]
A0,A1
NCS0
NCS2
NWE
MCK
NRD
One bit is dedicated to enable/disable NAND Flash scrambling and one bit is dedicated
enable/disable scrambling the off chip SRAM. When at least one external SRAM is scrambled,
the SMSC field must be set in the SMC_OCMS register.
When multiple chip selects (external SRAM) are handled, it is possible to configure the scram-
bling function per chip select using the OCMS field in the SMC_TIMINGS registers.
To scramble the NAND Flash contents, the SRSE field must be set in the SMC_OCMS register.
When NAND Flash memory content is scrambled, the on-chip SRAM page buffer associated for
the transfer is also scrambled.
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to
avoid bus contention or operation conflict.
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle
cycle ensures that there is no bus contention between the de-activation of one device and the
activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS1, NWR0 to
NWR1, NCS[0..3], and NRD lines. They are all set to 1.
Figure 25-13
Select 2.
NRD_CYCLE
illustrates a chip select wait state between access on Chip Select 0 and Chip
Read to Write
Wait State
Chip Select
Wait State
NWE_CYCLE
SAM3U Series
SAM3U Series
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