ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 444

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.3.4
26.3.5
26.3.5.1
26.3.5.2
26.3.5.3
26.3.5.4
444
SAM3U Series
Data Transfers
PDC Flags and Peripheral Status Register
Receive Transfer End
Transmit Transfer End
Receive Buffer Full
Transmit Buffer Empty
The serial peripheral triggers its associated PDC channels’ transfers using transmit enable
(TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the periph-
eral’s user interface.
When the peripheral receives an external data, it sends a Receive Ready signal to its PDC
receive channel which then requests access to the Matrix. When access is granted, the PDC
receive channel starts reading the peripheral Receive Holding Register (RHR). The read data
are stored in an internal buffer and then written to memory.
When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit chan-
nel which then requests access to the Matrix. When access is granted, the PDC transmit
channel reads data from memory and puts them to Transmit Holding Register (THR) of its asso-
ciated peripheral. The same peripheral sends data according to its mechanism.
Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the
PDC sends back flags to the peripheral. All these flags are only visible in the Peripheral Status
Register.
Depending on the type of peripheral, half or full duplex, the flags belong to either one single
channel or two different channels.
This flag is set when PERIPH_RCR register reaches zero and the last data has been transferred
to memory.
It is reset by writing a non zero value in PERIPH_RCR or PERIPH_RNCR.
This flag is set when PERIPH_TCR register reaches zero and the last data has been written into
peripheral THR.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
This flag is set when PERIPH_RCR register reaches zero with PERIPH_RNCR also set to zero
and the last data has been transferred to memory.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
This flag is set when PERIPH_TCR register reaches zero with PERIPH_TNCR also set to zero
and the last data has been written into peripheral THR.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
6430D–ATARM–25-Mar-11