ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 462

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.2
Figure 28-1. General Clock Block Diagram
28.3
462
XOUT32
(Supply Controller)
Block Diagram
XIN32
XOUT
Master Clock Controller
XIN
SAM3U Series
XTALSEL
Clock Generator
RC Oscillator
12/8/4 MHz
Embedded
Management
Embedded
32 kHz RC
3-20 MHz
Oscillator
32768 Hz
Status
Oscillator
Oscillator
Crystal
Controller
Crystal
Fast
Power
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is
the clock provided to all the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting
the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLLs.
The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a
Master Clock divider which allows the processor clock to be faster than the Master Clock.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the
selected clock between 1 and 64, and the division by 3. The PRES field in PMC_MCKR pro-
grams the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
Control
0
1
0
1
MOSCSEL
USB UTMI
PLLA and
Divider
PLL
UPLL Clock
UPLLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
Slow Clock
SLCK
UPLLDIV
/1,/2
MAINCK
UPLLCK
PLLACK
SLCK
Master Clock Controller
MAINCK
UPLLCK
PLLACK
/1,/2,/3,/4,...,/64
SLCK
MCK
Prescaler
Programmable Clock Controller
/1,/2,/4,...,/64
Prescaler
Sleep Mode
Processor
Clock Controller
Controller
ON/OFF
Divider
Clock
Peripherals
ON/OFF
/8
Free Running Clock
Processor Clock
6430D–ATARM–25-Mar-11
Master Clock
USB Clock
UDPCK
FCLK
HCLK
SysTick
MCK
int
periph_clk[..]
pck[..]