ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 389

Manufacturer Part Number

KIT EVAL FOR AT91SAM3U CORTEX

Manufacturer

Processor To Be Evaluated

Data Bus Width

Interface Type

Operating Supply Voltage

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

Board CD Docs

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Manufacturer

Part Number:

Manufacturer:

Figure 25-32. Write Enable Timing Configuration

Figure 25-33. Write Enable Timing for NAND Flash Device Data Input Mode.

6430D–ATARM–25-Mar-11

NFC Initialization

Prior to any Command and Data Transfer, the SMC User Interface must be configured to meet

the device timing requirements.

Use NWE_SETUP, NWE_PULSE and NWE_CYCLE to define the write enable waveform

according to the device datasheet.

Use TADL field in the SMC_TIMINGS register to configure the timing between the last address

latch cycle and the first rising edge of WEN for data input.

Use NRD_SETUP, NRD_PULSE and NRD_CYCLE to define the read enable waveform accord-

ing to the device datasheet.

Use TAR field in the SMC_TIMINGS register to configure the timings between address latch

enable falling edge to read enable falling edge.

Use TCLR field in the SMC_TIMINGS register to configure the timings between the command

latch enable falling edge to the read enable falling edge.

• Write enable Configuration

• Read Enable Configuration

SAM3U Series