ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 484

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.14.10 PMC Clock Generator PLLA Register
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in the
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
• DIVA: Divider
• PLLACOUNT: PLLA Counter
Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• MULA: PLLA Multiplier
0 = The PLLA is deactivated.
1 up to 2047 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1.
484
DIVA
0
1
2 - 255
31
23
15
–
–
7
SAM3U Series
CKGR_PLLAR
0x400E0428
Read-write
30
22
14
–
–
6
29
21
13
1
5
Divider Selected
Divider output is 0
Divider is bypassed (DIVA=1)
Divider output is the selected clock divided by DIVA
28
20
12
–
4
MULA
DIVA
“PMC Write Protect Mode
27
19
11
–
3
PLLACOUNT
26
18
10
2
Register”.
MULA
25
17
9
1
6430D–ATARM–25-Mar-11
24
16
8
0