ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 402
![KIT EVAL FOR AT91SAM3U CORTEX](/photos/9/20/92037/atsam3u-ek_sml.jpg)
ATSAM3U-EK
Manufacturer Part Number
ATSAM3U-EK
Description
KIT EVAL FOR AT91SAM3U CORTEX
Manufacturer
Atmel
Type
MCUr
Datasheets
1.ATSAM3U-EK.pdf
(2 pages)
2.ATSAM3U-EK.pdf
(61 pages)
3.ATSAM3U-EK.pdf
(1171 pages)
4.ATSAM3U-EK.pdf
(53 pages)
Specifications of ATSAM3U-EK
Contents
Board
Processor To Be Evaluated
SAM3U
Data Bus Width
32 bit
Interface Type
RS-232, USB
Operating Supply Voltage
3 V
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
SAM3U4E
Silicon Family Name
SAM3U
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT91SAM3U
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U-EK
Manufacturer:
Atmel
Quantity:
10
- ATSAM3U-EK PDF datasheet
- ATSAM3U-EK PDF datasheet #2
- ATSAM3U-EK PDF datasheet #3
- ATSAM3U-EK PDF datasheet #4
- Current page: 402 of 1171
- Download datasheet (25Mb)
25.18.1
Name:
Address:
Access:
Reset:
• PAGESIZE
This field defines the page size of the NAND Flash device.
• WSPARE: Write Spare Area
0: The NFC skips the spare area in write mode.
1: The NFC writes both main area and spare area in write mode.
• RSPARE: Read Spare Area
0: The NFC skips the spare area in read mode.
1: The NFC reads both main area and spare area in read mode.
• EDGECTRL: Rising/Falling Edge Detection Control
0: Rising edge is detected.
1: Falling edge is detected.
• RBEDGE: Ready/Busy Signal Edge Detection
0: When set to zero, RB_EDGE fields indicate the level of the Ready/Busy lines.
1: When set to one, RB_EDGE fields indicate only transition on Ready/Busy lines.
• DTOCYC: Data Timeout Cycle Number
402
402
Value
0
1
2
3
31
23
15
–
–
–
7
–
SAM3U Series
SAM3U Series
SMC NFC Configuration Register
SMC_CFG
0x400E0000
Read-write
0x00000000
30
22
14
–
–
6
–
PS512_16
PS1024_32
PS2048_64
PS4096_128
RBEDGE
DTOMUL
29
21
13
–
5
–
Name
EDGECTRL
28
20
12
–
4
–
Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes
Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes
Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes
Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes
27
19
11
–
–
3
–
Description
26
18
10
–
–
2
–
DTOCYC
RSPARE
25
17
–
9
1
PAGESIZE
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
WSPARE
24
16
–
8
0
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