ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 57

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2.4
13.2.4.1
13.2.4.2
13.2.4.3
13.2.4.4
13.3
13.3.1
13.3.1.1
13.3.1.2
13.3.1.3
6430D–ATARM–25-Mar-11
Programmers model
Cortex-M3 core peripherals
Processor mode and privilege levels for software execution
Nested Vectored Interrupt Controller
System control block
System timer
Memory protection unit
Thread mode
Handler mode
Unprivileged
These are:
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that sup-
ports low latency interrupt processing.
The System control block (SCB) is the programmers model interface to the processor. It pro-
vides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating Sys-
tem (RTOS) tick timer or as a simple counter.
The Memory protection unit (MPU) improves system reliability by defining the memory attributes
for different memory regions. It provides up to eight different regions, and an optional predefined
background region.
This section describes the Cortex-M3 programmers model. In addition to the individual core reg-
ister descriptions, it contains information about the processor modes and privilege levels for
software execution and stacks.
The processor modes are:
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
Used to handle exceptions. The processor returns to Thread mode when it has finished excep-
tion processing.
The privilege levels for software execution are:
The software:
• deterministic, high-performance interrupt handling for time-critical applications
• memory protection unit (MPU) for safety-critical applications
• extensive debug and trace capabilities:
• has limited access to the MSR and MRS instructions, and cannot use the CPS instruction
– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for
debugging and tracing.
SAM3U Series
57