ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 358

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.9
25.9.1
25.9.2
Figure 25-4.
Figure 25-5.
25.9.2.1
358
358
Connection to External Devices
SAM3U Series
SAM3U Series
Data Bus Width
Byte Write or Byte Select Access
Byte Write Access
Memory Connection for an 8-bit Data Bus
Memory Connection for a 16-bit Data Bus
A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by
the field DBW in SMC_MODE (Mode Register) for the corresponding chip select.
Figure 25-4
connect a 512K x 16-bit memory on NCS2.
Each chip select with a 16-bit data bus can operate with one of two different types of write
access: byte write or byte select access. This is controlled by the BAT field of the SMC_MODE
register for the corresponding chip select.
Byte write access supports one byte write signal per byte of the data bus and a single read
signal.
Note that the SMC does not allow boot in Byte Write Access mode.
• For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively, byte0
(lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided.
Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory.
SMC
SMC
shows how to connect a 512K x 8-bit memory on NCS2.
D[15:0]
NCS[2]
A[19:2]
NBS0
NBS1
NWE
A[18:2]
NCS[2]
NRD
D[7:0]
NWE
A1
NRD
A0
A1
D[7:0]
A[18:2]
Write Enable
Output Enable
Memory Enable
D[15:0]
A[18:1]
A[0]
Low Byte Enable
High Byte Enable
Write Enable
Output Enable
Memory Enable
A0
A1
Figure 25-5
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
shows how to