ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 655
ATSAM3U-EK
Manufacturer Part Number
ATSAM3U-EK
Description
KIT EVAL FOR AT91SAM3U CORTEX
Manufacturer
Atmel
Type
MCUr
Datasheets
1.ATSAM3U-EK.pdf
(2 pages)
2.ATSAM3U-EK.pdf
(61 pages)
3.ATSAM3U-EK.pdf
(1171 pages)
4.ATSAM3U-EK.pdf
(53 pages)
Specifications of ATSAM3U-EK
Contents
Board
Processor To Be Evaluated
SAM3U
Data Bus Width
32 bit
Interface Type
RS-232, USB
Operating Supply Voltage
3 V
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
SAM3U4E
Silicon Family Name
SAM3U
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT91SAM3U
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U-EK
Manufacturer:
Atmel
Quantity:
10
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33.10.6
Name:
Addresses: 0x40084020 (0), 0x40088020 (1)
Access:
Reset:
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in
page 646
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in
RXRDY behavior in Slave mode can be seen in
page 646
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in
6430D–ATARM–25-Mar-11
TXBUFE
31
23
15
–
–
7
–
and
and
TWI Status Register
TWI_SR
Read-only
0x0000F009
Figure 33-31 on page
Figure 33-31 on page
RXBUFF
OVRE
30
22
14
–
–
6
ENDTX
GACC
646.
646.
29
21
13
–
–
5
Figure 33-8 on page
Figure 33-10 on page
Figure 33-26 on page
ENDRX
SVACC
Figure 33-28 on page
Figure 33-8 on page 627
28
20
12
–
–
4
EOSACC
SVREAD
27
19
11
–
–
3
627.
628.
642,
644,
and in
Figure 33-29 on page
Figure 33-29 on page
SCLWS
TXRDY
26
18
10
–
–
2
Figure 33-10 on page
SAM3U Series
ARBLST
RXRDY
25
17
–
–
9
1
645,
645,
628.
Figure 33-30 on
Figure 33-30 on
TXCOMP
NACK
24
16
–
–
8
0
655
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