ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 592

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 32-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
32.7.3
592
592
SPCK cycle (for reference)
(from master)
(from slave)
(CPOL = 0)
(CPOL = 1)
(to slave)
SAM3U Series
SAM3U Series
Master Mode Operations
SPCK
SPCK
MOSI
MISO
NSS
*
When configured in Master Mode, the SPI operates on the clock generated by the internal pro-
grammable baud rate generator. It fully controls the data transfers to and from the slave(s)
connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock
signal (SPCK).
The SPI features two holding registers, the Transmit Data Register and the Receive Data Regis-
ter, and a single Shift Register. The holding registers maintain the data flow at a constant rate.
After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Trans-
mit Data Register). The written data is immediately transferred in the Shift Register and transfer
on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO
line is sampled and shifted in the Shift Register. Receiving data cannot occur without transmit-
ting data. If receiving mode is not needed, for example when communicating with a slave
receiver only (such as an LCD), the receive status flags in the status register can be discarded.
Before writing the TDR, the PCS field in the SPI_MR register must be set in order to select a
slave.
After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Trans-
mit Data Register). The written data is immediately transferred in the Shift Register and transfer
on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO
line is sampled and shifted in the Shift Register. Transmission cannot occur without reception.
Before writing the TDR, the PCS field must be set in order to select a slave.
If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is
completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data
in SPI_TDR is loaded in the Shift Register and a new transfer starts.
* Not defined but normally LSB of previous character transmitted.
1
MSB
MSB
2
6
6
3
5
5
4
4
4
5
3
3
6
2
2
7
1
1
8
LSB
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
LSB