ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 977

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

39.7.4
Name:
Address:
Access:
• SPEED: Speed Status
0 = reset by hardware when the hardware is in Full Speed mode.
1 = set by hardware when the hardware is in High Speed mode
• DET_SUSPD: Suspend Interrupt
0 = cleared by setting the DET_SUSPD bit in UDPHS_CLRINT register
1 = set by hardware when a UDPHS Suspend (Idle bus for three frame periods, a J state for 3 ms) is detected. This triggers
a UDPHS interrupt when the DET_SUSPD bit is set in UDPHS_IEN register.
• MICRO_SOF: Micro Start Of Frame Interrupt
0 = cleared by setting the MICRO_SOF bit in UDPHS_CLRINT register.
1 = set by hardware when an UDPHS micro start of frame PID (SOF) has been detected (every 125 us) or synthesized by
the macro. This triggers a UDPHS interrupt when the MICRO_SOF bit is set in UDPHS_IEN. In case of detected SOF, the
MICRO_FRAME_NUM field in UDPHS_FNUM register is incremented and the FRAME_NUMBER field doesn’t change.
Note:
• INT_SOF: Start Of Frame Interrupt
0 = cleared by setting the INT_SOF bit in UDPHS_CLRINT.
1 = set by hardware when an UDPHS Start Of Frame PID (SOF) has been detected (every 1 ms) or synthesized by the
macro. This triggers a UDPHS interrupt when the INT_SOF bit is set in UDPHS_IEN register. In case of detected SOF, in
High Speed mode, the MICRO_FRAME_NUMBER field is cleared in UDPHS_FNUM register and the FRAME_NUMBER
field is updated.
• ENDRESET: End Of Reset Interrupt
0 = cleared by setting the ENDRESET bit in UDPHS_CLRINT.
1 = set by hardware when an End Of Reset has been detected by the UDPHS controller. This triggers a UDPHS interrupt
when the ENDRESET bit is set in UDPHS_IEN.
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
UPSTR_RES
31
23
15
–
–
–
7
The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt (INT_SOF) are not generated at the same
time.
UDPHS Interrupt Status Register
UDPHS_INTSTA
0x400A4014
Read-only
ENDOFRSM
DMA_6
EPT_6
30
22
14
–
6
WAKE_UP
DMA_5
EPT_5
29
21
13
–
5
ENDRESET
DMA_4
EPT_4
28
20
12
–
4
INT_SOF
DMA_3
EPT_3
27
19
11
–
3
MICRO_SOF
DMA_2
EPT_2
26
18
10
–
2
DET_SUSPD
SAM3U Series
SAM3U Series
DMA_1
EPT_1
25
17
–
9
1
SPEED
EPT_0
24
16
–
–
8
0
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