ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 548

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

31.7.1.4
31.7.2
548
548
SAM3U Series
SAM3U Series
Transmitter Operations
Serial Clock Ratio Considerations
Figure 31-7. Receiver Clock Management
The Transmitter and the Receiver can be programmed to operate with the clock signals provided
on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In
this case, the maximum clock speed allowed on the RK pin is:
In addition, the maximum clock speed allowed on the TK pin is:
A transmitted frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR).
“Start” on page 550.
The frame synchronization is configured setting the Transmit Frame Mode Register
(SSC_TFMR).
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and
the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR
register then transferred to the shift register according to the data format selected.
When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is
set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register,
the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding
register.
– Master Clock divided by 2 if Receiver Frame Synchro is input
– Master Clock divided by 3 if Receiver Frame Synchro is output
– Master Clock divided by 6 if Transmit Frame Synchro is input
– Master Clock divided by 2 if Transmit Frame Synchro is output
Transmitter
RK (pin)
Divider
Clock
Clock
See “Frame Sync” on page 552.
MUX
CKS
CKO
Controller
Tri-state
MUX
CKI
INV
Data Transfer
Controller
Tri-state
CKG
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Clock
Output
Receiver
Clock
See