PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 143

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 1:
RESET_IN_N
POR_IN_N
Reset Module Block Diagram
2.1 RESET_IN_N or POR_IN_N?
Reset module
Watch Dog Timer
Interrupt Counter
Figure 1
PNX15xx/952x Series system.
POR_IN_N is meant to be used at power up of the system. By asserting this pin low
as soon as the power sequencing starts ensures limited (if not none) contentions
inside the PNX15xx/952x Series system as well as the PNX15xx/952x Series pin
level. Furthermore by resetting the JTAG state machine the POR_IN_N signal
ensures the PNX15xx/952x Series pins start with the correct mode. This is the cold
reset and must always be connected.
RESET_IN_N is complementary to the POR_IN_N signal and could be referenced as
the warm reset. A typical application where the feature can be used is a system board
where the JTAG boundary scan is to be used to reset PNX15xx/952x Series without
executing a full power down and up sequence. In this case the PNX15xx/952x Series
JTAG state machine should not be reset. Since all PNX15xx/952x Series pins can
become outputs in boundary scan mode it is possible to assert a 0 on the
RESET_IN_N pin while the PNX15xx/952x Series system is still under the control of
the internal JTAG state machine. This pin may not be connected at board level.
RST_CAUSE
Bus Interface
RST_CTL
Registers
shows an overview of the Reset module connections to the remaining of the
sys_rst_out_n
(to off-chip
devices)
Rev. 4.0 — 03 December 2007
peri_rst_n
DCS Bus
PNX15xx/952x Series
Test block
TM3260
int_rst_n
Module 2
Module N
Module 1
int_rst1_n
int_rst2_n
int_rst_n
int_rst_n
jtag_rst_n
© NXP B.V. 2007. All rights reserved.
Chapter 4: Reset
4-143