PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 134

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
8. Miscellaneous
PNX15XX_PNX952X_SER_N_4
Product data sheet
Several other system MMIO registers are described in the following paragraphs and
detailed in the next
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By default PCI_INTA_N is an input/output pin used in open drain mode for the
PCI bus. When a host CPU wants to assert an interrupt to the TM3260 it asserts
the PCI_INTA_N low. Similarly if TM3260 wants to notify a host CPU of an
interrupt it can assert low the PCI_INTA_N pin by programming the PCI_INTA
MMIO register.
The 8 SCRATCH MMIO registers are mainly used for debug purpose. Since they
are not reset by the external POR_IN_N or RESET_IN_N signals they can be
used for post-mortem system crash to retain some critical or debug values.
Event timestamping for the SPDI interface comes with a diversity of
requirements. To keep PNX15xx/952x Series as a programmable system, a
system multiplexer is implemented to select which event or signal to timestamp.
The multiplexer is controlled by the SPDI_MUX_SEL MMIO register. The different
selectable signals coming from the SPDI module are displayed in
The SPARE_CTRL MMIO register is reserved for future usage.
Rev. 4.0 — 03 December 2007
Section
8.1:
Chapter 3: System On Chip Resources
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
Section
8.1.
3-134