PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 184

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
PLL Registers
Offset 0x04,7000
Reset values set for expected frequencies for faster boot-up, shorter boot code.
31:30
29
28
27:24
23:21
20:12
11:10
9:4
3:2
1
0
Offset 0x04,7004
Reset values set for expected frequencies for faster boot-up, shorter boot code.
31:30
29
28
27:24
23:21
20:12
11:10
9:4
3:2
1
0
Symbol
Reserved
Turn Off Acknowledge
PLL Lock
pll0_adj
Reserved
pll0_n
Reserved
pll0_m
pll0_p
pll0_pd
pll0_bp
Reserved
Turn Off Acknowledge
PLL Lock
pll1_adj
Reserved
pll1_n
Reserved
pll1_m
pll1_p
pll1_pd
pll1_bp
3.2 Registers Description
PLL0_CTL
PLL1_CTL
Acces
s
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
-
-
-
0
-
0x4A
-
0x5
0
0
1
-
-
-
4
-
0x22
-
6
2
0
1
Rev. 4.0 — 03 December 2007
Description
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Indicates that during a frequency change that the clock has been
driven low.
A ‘1’ indicates that the PLL is locked
Current adjustment.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
9-bit N parameter to PLL0
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
6-bit M parameter to PLL0.
2-bit P parameter to PLL0.
1: powerdown PLL0
0: Do not bypass the DDS
1: Bypass the DDS and use the xtal (27 MHz). Normal Operating
mode.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Indicates that during a frequency change that the clock has been
driven low.
A ‘1’ indicates that the PLL is locked
Current adjustment.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
9-bit N parameter to PLL1.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
6-bit M parameter to PLL1.
2-bit P parameter to PLL1.
1: powerdown PLL1
0: Do not bypass the DDS.
1: Bypass the DDS and use the xtal (27 MHz)
Section 2.2.1 on page
Section 2.2.1 on page
Section 2.2.1 on page
Section 2.2.1 on page
Section 2.2.1 on page
Section 2.2.1 on page
Section 2.2.1 on page
PNX15xx/952x Series
Chapter 5: The Clock Module
5-158.
5-158.
© NXP B.V. 2007. All rights reserved.
5-158.
5-158.
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