PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 14

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Chapter 1: Integrated Circuit Data
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Chapter 2: Overview
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Chapter 3: System On Chip Resources
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Chapter 4: Reset
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Chapter 5: The Clock Module
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PNX15XX_PNX952X_SER_N_4
Product data sheet
Application Diagram of the Crystal Oscillator
52
SSTL_2 Test Load Condition
SSTL_2 Receiver Signal Conditions
BPX2T14MCP Test Load Condition
BPTS1CHP and BPTS1CP Test Load Condi-
tion
BPTS3CHP and BPTS3CP Test Load Condi-
tion
BPT3MCHDT5V and BPT3MCHT5V Test
Load Condition
PCI Tval(min) and Slew Rate Test Load Con-
dition
Reset Timing
PCI Output and Input Timing Measurement
Conditions
PCI Tval(max) Rising and Falling Edge
QVCP and FGPO I/O Timing
VIP and FGPI I/O Timing
Block Diagram PNX15xx/952x Series
The Two Operating Modes of PNX15xx/952x
Series
PNX15xx/952x Series System Memory Map
Reset Module Block Diagram
Watchdog in Non Interrupt Mode
Clock Module Block Diagram
PLL Block Diagram
Block Diagram of the Clock Control Logic
Waveforms of the Blocking Logic
Clock Stretcher
Clock Detection Circuit
TM3260, DDR and QVCP clocks
QVCP_PROC Clock
QVCP_PIX Clock
Clock Dividers
Internal PNX15xx/952x Series Clock from Di-
viders
Internal PNX15xx/952x Series Clock from Di-
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Rev. 4.0 — 03 December 2007
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PNX15xx/952x Series
LAN 10/100 I/O Timing in MII Mode
LAN 10/100 I/O Timing in RMII Mode
Audio Input I/O Timing
Audio Output I/O Timing
SPDIF I/O Timing
I2C I/O Timing
I2C I/O Timing
Audio Output I/O Timing
JTAG I/O Timing
BGA456 Plastic Ball grid Array; 456 Balls;
body 27 x 27 x 1.75 mm
BGA Bottom View Pin Assignment
BGA Top View Pin Assignment
Digital VCCP Power Supply to Analog VCCA/
VSSA Power Supply Filter
Digital VDD Power Supply to Analog VDDA/
VSSA_1.2 Power Supply Filter
Digital VDD Power Supply to Analog VDDA/
VSSA_1.2 Power Supply Filter
PNX15xx/952x Series Functional Block Dia-
gram
112
Simplified Internal Bus Infrastructure
Watchdog in Interrupt Mode
POR_IN_N Timing and Reset Sequence
viders: PCI, SPDI, LCD and I2C
Internal PNX15xx/952x Series Clock from Di-
viders: LCD Timestamp
GPIO Clocks
VDI_CLK1 Block Diagram
VDI_CLK2 Block Diagram
VDO_CLK1 Block Diagram
VDO_CLK2 Block Diagram
AO Clocks
AI Clocks
PHY LAN Clock Block Diagram
Receive and Transmit LAN Clocks
SPDO Clock
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Connected Media Processor
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© NXP B.V. 2007. All rights reserved.
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