PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 300

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 11: Signal and Event Monitoring Control Registers for the Timestamp Units
Table 12: Timestamp Unit Registers
Table 13: GPIO Time Counter
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
Offset 0x10,4034-> 0x060
31:10
9:2
1:0
a
Offset 0x10,40C4->0x0F0
31
30:0
Offset 0x10,40F4
31
30:0
Bit
Bit
IO_SEL cannot be written to unless timestamping is disabled (EVENT_MODE=00).
Symbol
Unused
IO_SEL
EVENT_MODE
Symbol
Direction
Timestamp
Symbol
Unused
TIME_CTR
a
4.5 Signal and Event Monitoring Control Registers for the Timestamp
4.6 Timestamp Unit Registers
4.7 GPIO Time Counter
TIME_CTR
Units
TSU<0-11>
GPIO_EV<4-15>
Acces
s
R/W
R/W
Acces
s
R
R
Acces
s
R
Value
-
0
0
Value
0
0
Value
-
0
Rev. 4.0 — 03 December 2007
Description
This field selects the GPIO pin or internal global signal to be
monitored. Refer to
Timestamping event mode:
Description
This field indicates the direction of the event which occurred:
This field holds the 31-bit timestamp.
Description
GPIO master time counter. This counter is incremented at a
frequency of 13.5 MHz.
00 - event detection disabled
01 - capture negative edge
10 - capture positive edge
11 - capture either edge
0 - a falling edge
1 - a rising edge
Chapter 8: General Purpose Input Output Pins
Section 4.15
PNX15xx/952x Series
for field values.
© NXP B.V. 2007. All rights reserved.
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