PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 161
PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
Specifications of PNX1500E
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Table 6: DDS and PLL Clock Assignment
PNX15XX_PNX952X_SER_N_4
Product data sheet
Source
PLL0
PLL1
PLL2
DDS0/PLL0
DDS1/PLL1
DDS2
DDS3
DDS4
DDS5
DDS6
DDS7
DDS8
Destinations
clk_tm
clk_fgpo
clk_mem
clk_tm
clk_fgpo
clk_fgpo
ao_osclk
ai_osclk
clk_spdo
clk_gpio_q6_12
clk_vip
clk_gpio_q4
2.2.3 The DDS Clocks
2.2.4 DDS and PLL Assignment Summary
The DDS clocks are recommended for clocks that need to track dynamically another
frequency by very small steps. The following equations characterize the PNX15xx/
952x Series DDS blocks:
registers
The
952x Series system.
F
step
jitter
DDS
Figure 6
=
=
=
1.728GHz
-------------------------
1.728GHz N
----------------------------------- -
-------------------------
1.728GHz
clk_lan
clk_lan
clk_gpio_14
clk_lan
clk_gpio_13
clk_gpio_q5
clk_fgpi
2
32
1
2
summarizes the assignment of the different DDSes of the PNX15xx/
32
Rev. 4.0 — 03 December 2007
=
=
0.4Hz
0.579ns
, where N is a 31-bit value stored in the DDS[8:0]_CTL MMIO
clk_qvcp_out
clk_qvcp_out
clk_lan
ao_osclk
ao_osclk
PNX15xx/952x Series
Chapter 5: The Clock Module
© NXP B.V. 2007. All rights reserved.
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