PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 672

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 2:
MIIM
(R)MII Tx
(R)MMI Rx
LAN100 Functional Block Diagram
Tx Data
Tx Status
2.2 Functional Block Diagram
Figure 2
LAN100. Primary components of the LAN100, shown as blocks outlined in black, are
described below. The Transmit Datapath and Receive Datapath are shown with
unoutlined background colors.
The registers provide MMIO acces to the LAN100. They interface to the transmit and
receive data-paths, and to the MII Interface.
The MII Interface connects the LAN100 to the off-chip PHY.
The Transmit Datapath has two transmit DMA managers, DMA0 and DMA1, which
read descriptors and data from memory and write status to memory. In real-time
mode, DMA0 can be used to handle real-time transmissions and DMA1 can be used
to handle non-real-time transmissions. In Quality-of-Service (QoS) mode, DMA0 has
the lowest priority and DMA1 has the highest priority.
Transmission from both of the transmit DMA managers is mediated by arbitration
logic, including:
•
•
•
Multiplexers to select one of the transmit DMA managers
Transmit Retry module to handle Ethernet retry and abort conditions
Transmit Flow Control module to insert Ethernet pause frames where needed.
Pause frame insertion
Transmit Datapath
Buffer and abort logic
Pass or block packets
Tx Flow Control
shows a more detailed block diagram of the main internal units of the
Rx Buffer
Tx Retry
Tx Retry
Rx Filter
Module
Abort
Rev. 4.0 — 03 December 2007
Chapter 23: LAN100 — Ethernet Media Access Controller
Receive Datapath
Time-stamp and
QoS Arbiter
Device Registers
LAN100
PNX15xx/952x Series
Tx DMA0
Tx DMA0
Tx DMA1
Tx DMA1
Rx DMA
Rx DMA
© NXP B.V. 2007. All rights reserved.
Descriptors
Data
Status
Descriptors
Data
Status
Descriptors
Data
Status
MMIO
Control
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