PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 591

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.4.10 Interrupt Generation
2.4.9 Address Generation
Each of the three video planes is assigned a set of two base address registers and
two line address pointers. Depending on the base address mode, video data
corresponding to each plane is written using one pointer, or using both pointers
alternating on each line. At the end of the line, the pitch value is added to the active
line address pointer. The pitch defines the difference in the address of two vertically
adjacent pixels. The pitch values are defined separately for chroma and luma
components only. The lower three bits of the first three base address registers are
used as an intra-long-word offset for the leftmost pixel components of each line. The
offset has to be a multiple of the number of bytes per component.
The following interrupt events are defined:
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TASK_ERROR
Current processing task leads to a pipeline error, MBS has to be reset to resume
with new scaling task(s).
TASK_END
Current task processing is done, but some data might still remain in the output
FIFO - this Interrupt denotes the point when the MBS is ready to start the
processing of a new task.
TASK_OVERFLOW
Task fifo overflow - task request written into Task- fifo-register got ignored.
TASK_IDLE
Task finished and the task fifo is empty.
TASK_EMPTY
Task fifo runs empty - generation of this interrupt requires that there was a
pending task in the task fifo. This interrupt will not be generated if tasks are only
submitted in the MBS idle state.
TASK_DONE
Current task finished and all writes complete - on reception of this interrupt, all
data will be accessible in the main memory.
Rev. 4.0 — 03 December 2007
Chapter 19: Memory Based Scaler
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
19-591