PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 37

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 4: PNX1500 Interface
PNX15XX_PNX952X_SER_N_4
Product data sheet
Pin Name
VDO_CLK2
VDO_AUX
FGPO_REC_SYNC
FGPO_BUF_SYNC
Octal Audio In (audio in always acts as receiver, but can be set as master or slave for A/D timing)
AI_OSCLK
AI_SCK
BGA
Ball
AD20
AF23
C17
B19
E24
A18
Pad
Type
BPX2T14MCP
BPX2T14MCP
BPX2T14MCP
BPTS1CHP
BPTS1CHP
BPTS1CHP
Rev. 4.0 — 03 December 2007
I/O
Type
OUT
OUT
I/O
I/O
I/O
I/O
GPIO
#
55
60
-
-
-
-
P Description
U A positive edge on this internally or externally
D VDO_AUX can be programmed to output, a
D Synchronization signal for Streaming Parallel Data
D Synchronization signal for Streaming Parallel Data
U Over-Sampling Clock. This output can be
U AI can operate in either master or slave mode.
generated clock causes transitions of the streaming
data samples. When generated internally, the clock
can be software adjusted with sub one Hertz
accuracy to allow generation of a precisely timed
sequence of samples locked to an arbitrary
reference, such as a broadcast transport stream
source. A board level 27-33
recommended to reduce ringing.
CBLANK signal, a Field indicator or a video/
graphics detector.
Outputs. The FGPO data bit 5 is intended for the
extended mode.
Outputs. The FGPO data bit 6 is intended for the
extended mode.
programmed to emit any frequency up to 50 MHz
with a sub one Hertz resolution. It is intended to be
used as the 256 f
the external A/D subsystem. A board level 27-33
series resistor is recommended to reduce ringing.
AI_SCK is limited to 25 MHz. The sample rate of
valid samples embedded is variable. If used as a
output, a board level 27-33
recommended to reduce ringing.
• When Audio-In is programmed as the serial-
• When Audio In is programmed as the serial-
interface timing slave (power-up default),
AI_SCK is an input. AI_SCK receives the serial
bit clock from the external A/D subsystem. This
clock is treated as fully asynchronous to the
PNX1500 main clock.
interface timing master, AI_SCK is an output.
AI_SCK drives the serial clock for the external A/
D subsystem. The frequency is a programmable
integral divide of the AI_OSCLK frequency.
PNX15xx/952x Series
Chapter 1: Integrated Circuit Data
s
or 384 f
s
over sampling clock by
series resistor is
series resistor is
© NXP B.V. 2007. All rights reserved.
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