PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 110

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.1 The PCI View
Before going into the details of the three different views the following generic rules
should be noted:
These apertures need to be programmed at boot time or by the host before the
system can be operational. The internal boot scripts have pre-defined values for
these apertures (refer to
The PCI module provides three different apertures to the external PCI bus masters:
Any supported request on the PCI bus that falls outside of these three apertures is
discarded by the PCI module and therefore does not interfere with the PNX15xx/952x
Series system.
In addition PCI transactions to the XIO aperture from external PCI agents are
discarded.
Figure 2
PNX15xx/952x Series system. The apertures can be placed in any order with respect
to each other.
The aperture locations is programmed by the host CPU.
The aperture sizes can be programmed at boot time via some GPIO/BOOT_MODE[]
pins as defined in
CPU using PCI configuration cycles.
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The three views must be consistent. For example, it is not allowed to have a
different DRAM aperture location for the TM3260 CPU and the PCI module.
The apertures are “naturally aligned”. For example a 32-Megabyte aperture has a
starting address that is a multiple of 32 Megabytes.
Each aperture can be located anywhere in the 32-bit addressing space.
All the modules in the PNX15xx/952x Series SOC sees the same memory map,
i.e. an address represents an unique location for all the modules.
the MMIO aperture, used to access all the internal PNX15xx/952x Series
registers. See
the DRAM aperture, used to access to the main memory of PNX15xx/952x
Series.
the XIO aperture, used by TM3260 to access low speed slave devices like Flash
memories or IDE disk drives.
The MMIO aperture is starting at the address contained in the BASE_14 PCI
configuration space register.
The DRAM aperture is starting at the address contained in the BASE_10 PCI
configuration space register.
The XIO aperture is starting at the address contained in the BASE_18 PCI
configuration space register.
presents the memory map seen by the PCI module and the remaining of the
Rev. 4.0 — 03 December 2007
Chapter 6 Boot Module
Section 11. on page 3-139
Chapter 6 Boot
Module).
or they can be programmed by the host
Chapter 3: System On Chip Resources
for offset allocation per module.
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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