PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 23

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Chapter 22: Digital Video Disc Descrambler
Chapter 23: LAN100 — Ethernet Media Access Controller
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Chapter 24: TM3260 Debug
Table 1:
Table 2:
Table 3:
Chapter 25: I
Table 1:
Table 2:
Table 3:
Table 4:
Chapter 26: Memory Arbiter
Table 1:
Table 2:
Chapter 27: Power Management
Chapter 28: Pixel Formats
Table 1:
Chapter 29: Endian Mode
Table 1:
Table 2:
PNX15XX_PNX952X_SER_N_4
Product data sheet
Software Reset Procedure
VLD STATUS
VLD Control
VLD Commands
VLD Command Register
References for the MPEG-2 Macroblock
LAN100 MMIO Register Map
LAN100 Registers
PatternMatchJoin Register Nibble Functions
695
Receive Descriptor Structure
Receive Descriptor Control Word
Receive Status Structure
JTAG TM3260 Instruction Encoding
JTAG Instruction Encoding
Transfer of Data In via JTAG
Register Summary
IIC Registers
IIC Registers
IIC Registers
Peripheral ID and Sub-Arbitration
Register Summary
Native Pixel Format Summary
Memory Result of a Store to Address ‘a’
Instruction
Register Result of an (Unsigned) Load
2
C Interface
805
. . . . . . . . . . . . . . . . . . . . . . . . . . . 654
. . . . . . . . . . . . . . . . . . . . . . . . . . 765
. . . . . . . . . . . . . . . . . . . . . . . . . . 767
. . . . . . . . . . . . . . . . . . . . . . . . . . 768
. . . . . . . . . . . . . . . . . . . . . . . . . 653
. . . . . . . . . . . . . . . . . . . . . . . 656
. . . . . . . . . . . . . . . . . . . . . 678
. . . . . . . . . . . . . . . . . . . . . 764
. . . . . . . . . . . . . . . . . . . . . 782
. . . . . . . . . . . . . . . . 657
. . . . . . . . . . . . . . . 698
. . . . . . . . . . . . . . 652
. . . . . . . . . . . . . . 750
. . . . . . . . . . . . 675
. . . . . . . . . . . . 697
. . . . . . . . . . . . 752
. . . . . . . . . . . 789
. . . . . . . . 697
. . . . . . . . 777
Rev. 4.0 — 03 December 2007
. . . . . . 750
.
Table 7:
Table 8:
Table 9:
Table 10:
Table 7:
Table 8:
Table 9:
Table 10:
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Table 12:
Table 4:
Table 5:
Table 5:
Table 6:
Table 7:
Table 3:
Table 2:
Table 3:
PNX15xx/952x Series
Header Data
References for the MPEG-1 Macroblock
Header Data
VLD Error Handling
Register Summary
VLD Registers
Receive Status Information Word
Transmit Descriptor Fields
Transmit Descriptor Control Word
Transmit Status Structure
Transmit Status Information Word
LAN100 Pin Interface to external PHY
Register Summary
TM_DBG 1 Registers
Status Codes
IIC Registers
IIC Registers
PMAN (Hub) Arbiter Registers
Alpha Code Value and Pixel Transparency
798
Instruction
Register Result of a (Signed) Load Instruction
806
805
Connected Media Processor
659
661
. . . . . . . . . . . . . . . . . . . . . . . . . 768
. . . . . . . . . . . . . . . . . . . . . . . . . 773
. . . . . . . . . . . . . . . . . . . . . . . . . 774
. . . . . . . . . . . . . . . . . . . . . . . . 664
. . . . . . . . . . . . . . . . . . . . 663
. . . . . . . . . . . . . . . . . . . . 755
. . . . . . . . . . . . . . . . . . . 662
. . . . . . . . . . . . . . . . . . 756
© NXP B.V. 2007. All rights reserved.
. . . . . . . . . . . . . . 701
. . . . . . . . . . . . . 700
. . . . . . . . . . 782
. . . . . . . 698
. . . . . . . 701
. . . . . . . 702
. . . 742
-xxiii
. .