PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 810

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
6. Implementation Details
PNX15XX_PNX952X_SER_N_4
Product data sheet
6.1 PMAN Network Endian Block Diagram
The PNX15xx/952x Series system has two different bus structures:
The system endian mode of operation is designated to each component by the
system big-endian signal - ’1’ for big-endian mode, ’0’ for little-endian mode.
Referring to
data transfers across a standard 32-bit “DTL interface.” Module 1 uses the data
ordering rules according to
according to
data format to address invariant format (this is done in the "Endian Swap" portion of
the PMAN structure) while Module 2 does not require any such conversion (the
module is already in the address invariant format). The rest of the PMAN and
memory interface structure is address invariant.
The PMAN Endian Swap unit (as shown for Module 1) or the Module endian swap
unit (as shown in Module 2), must deal with unit endian swapping and unit packing .
Swapping is defined as “positioning each byte of a unit correctly with respect to the
memory byte address that it is supposed to go to.” Swapping is what implements the
CPU rule. Packing is defined as “the action that places consecutive units
simultaneously on a wider bus in order to implement the DMA rule.”
The DMA module need not be aware of the details of either the DTL, or the MTL Bus.
It just swaps and packs, based on its knowledge of unit size and system endian
mode, and creates the valid DTL interface data.
Figure 6:
•
•
AI_STATUS (r/w)
Device Control and Status Network, or DCS Network; and
Pipelined Memory Access Network, or PMAN Network, or MTL bus.
AI_CTL (r/w)
CAP_ENABLE
SIGN_CONVERT
CAP_MODE
RESET
Audio In Control/Status MMIO Registers
Figure
Table
DIAG_MODE
Rev. 4.0 — 03 December 2007
6. The PMAN interface to Module 1 therefore has to convert the
1, note that both modules are identical. They perform all DMA
31
31
Table 5
27
27
while Module 2 uses the address invariance rules
23
23
19
19
HBE (Highway bandwidth error)
PNX15xx/952x Series
15
15
RESERVED
OVR_INTEN
HBE_INTEN
BUF2_INTEN
BUF1_ACTIVE
BUF1_INTEN
Chapter 29: Endian Mode
11
11
OVERRUN
ACK_OVR
BUF2_FULL
ACK_HBE
BUF1_FULL
© NXP B.V. 2007. All rights reserved.
7
7
ACK2
ACK1
3
3
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