PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 271
PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
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Table 3: Settings for MASK[xx] and IOD[xx] Bits
PNX15XX_PNX952X_SER_N_4
Product data sheet
MASK[xx] Bit
0
0
1
1
Note: The xx portion of MASK[xx] or IOD[xx] identifies the GPIO number of the particular pin. Refer to
number allocation and the GPIO Data Control Register table on
IOD[xx] Bit
0
1
0
1
bit[16] is paired with IOD bit[0] and [17]...[1], [18]...[2], etc. This pairing makes up the
2-bit value for programming the GPIO data setting. The pairing allows to control 16
GPIO pins with a single 32-bit MMIO write/read from the TM3260 CPU. The available
data settings are documented in
Section
Remark: Software should treat with care these MMIO registers since they do not
behave as regular registers and some electrical problem can occur at board level
since:
Writing Data on a GPIO Pin
A specific data can be written to a GPIO pin by executing a single MMIO register
write. This is achieved by setting a ‘1’ to the corresponding MASK[xx] bit and set IOD
bit to the desired pin value, as described in
Remark: The IOD bits may not reflect the value written to them since these bits are
used to always represent the actual signal values at the pin side.
Remark: After reset every GPIO pin is in GPIO mode. The GPIO mode settings need
to be programmed in order to switch the GPIO into its primary operating mode. It
should be noted that if the primary operating mode for a GPIO is an active-low output
a glitch can occur on the output if the data reaches the IO logic before the output
enable. Therefore the software should always program it to GPIO mode first and then
switch it to primary operating mode as follows:
1. Program Mode Select register in GPIO mode, i.e. 10 (binary).
2. Program Mode Select register in primary operating mode, i.e. 01 (binary).
•
•
•
Description
Retain current stored data (a write of 00 does not overwrite current data). Not Readable.
Data Input Mode, i.e. set the corresponding GPIO Pin in tri-state mode.
GPIO Output Mode. Drive a ‘0’ onto the corresponding GPIO Pin or a generated pattern
(see
GPIO Output Mode. Drive a ‘1’ onto the corresponding GPIO Pin or a generated pattern
(see
Note: if open-drain mode is selected, drive to ‘1’ is disabled.
writing to these bits may switch I/O signals between input & output mode.
the IOD field of these registers reflects the state of the actual pad of the signal.
This implies that depending on the mode of the GPIO pin values written to the
IOD bits may not affect the pin state, and therefore cannot be read back.
writing a 00 (binary) value to a MASK and IOD field pair causes no changes to
the 2-bit field.
Section
Section
4.2.
2.3)
2.3).
Rev. 4.0 — 03 December 2007
page
Table
Chapter 8: General Purpose Input Output Pins
8-269.
3. The complete MMIO register layouts are in
Table
PNX15xx/952x Series
3.
Table 1
© NXP B.V. 2007. All rights reserved.
for the
8-271
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