PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 6
PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
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NXP Semiconductors
Volume 1 of 1
4.11
4.12
Chapter 9: DDR Controller
1.
2.
2.1
2.1.1
2.1.2
2.1.3
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.3
2.3.1
2.3.2
2.4
2.5
2.5.1
2.5.2
2.5.3
2.5.4
Chapter 10: LCD Controller
1.
1.1
2.
2.1
2.2
3.
3.1
3.2
Chapter 11: QVCP
1.
1.1
2.
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
PNX15XX_PNX952X_SER_N_4
Product data sheet
Introduction
Functional Description
Introduction
Functional Description
Operation
Introduction
Functional Description
GPIO Interrupt Registers for the FIFO Queues
(One for each FIFO Queue)
GPIO Module Status Register for all 12
Timestamp Units
Start and Warm Start
The Start Mode
Warm Start
Observing Start State
Arbitration
The First Level of Arbitration: Between the DMA
and the CPU
Second Level of Arbitration
Dynamic Ratios
Pre-Emption
Back Log Buffer (BLB)
PMAN (Hub) versus DDR Controller Interaction
321
Addressing
Memory Region Mapping Scheme
DDR Memory Rank Locations
Clock Programming
Power Management
Halting and Unhalting
MMIO Directed Halt
Auto Halt
Observing Halt Mode
LCD Controller Features
Overview
Power Sequencing
Overview
Power Sequencing State Machine
Features
QVCP Block Diagram
Architecture
Layer Resources and Functions
Memory Access Control (DMA CTRL)
Pixel Formatter Unit (PFU)
Chroma Key and Undither (CKEY/UDTH) Unit
Chroma Upsample Filter (CUPS)
Linear Interpolator (LINT)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
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315
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304
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303
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Rev. 4.0 — 03 December 2007
. . . . . . . 358
359
. .
4.13
4.14
4.15
2.5.5
3.
3.1
3.2
3.3
3.4
3.5
3.6
4.
4.0.1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5.
5.1
5.2
6.
3.2.1
3.2.2
3.2.3
3.2.4
3.3
3.4
4.
4.1
2.3.6
2.3.7
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
Application Notes
Timing Diagrams and Tables
Register Descriptions
References
Register Descriptions
PNX15xx/952x Series
GPIO POWERDOWN
GPIO Module ID
GPIO IO_SEL Selection Values
Sequence of Actions
Memory Configurations
Error Signaling
Latency
Data Coherency
Programming the Internal Arbiter
The DDR Controller and the DDR Memory
Devices
Tcas Timing Parameter
Trrd and Trc Timing Parameters
Trfc Timing Parameter
Twr Timing Parameter
Tras Timing Parameter
Trp Timing Parameter
Trcd_rd Timing Parameter
Trcd_wr Timing Parameter
Register Summary
Register Table
IDLE state
DCEN state
BLEN state
PEPED state
Counter
Gating Logic
LCD MMIO Registers
Video/Graphics Contrast Brightness Matrix
(VCBM)
Layer and Fetch Control
Pool Resources and Functions
CLUT (Color Look Up Table)
DCTI (Digital Chroma/Color Transient
Improvement)
HSRU (Horizontal Sample Rate Upconverter)
HIST (Histogram Modification) Unit
LSHR (Luminance/Luma Sharpening) Unit
Color Features (CFTR) Unit
332
363
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
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365
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. . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Connected Media Processor
. . . . . . . . . . . . . . . . . . . . . . . . . . 330
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. . . . . . . . . . . . . . . . . . . 335
. . . . . . . . . . . . . . . . . . . 350
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. . . . . . . . . . . . . . . . . 335
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© NXP B.V. 2007. All rights reserved.
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365
-vi
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