PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 752
PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
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PNX15XX_PNX952X_SER_N_4
Product data sheet
3.2 Debug Settings
Transfer of Data to TM3260 via JTAG
Poll control register to check if input buffer is empty or not and scan in data when it is
empty and set the ifull control bit to 1 triggering an interrupt. Note that scanning in any
instruction automatically scans out the 3 least significant bits (including the ifull or
ofull bit) of the selected TM_DBG_CTRL register.
Table 3: Transfer of Data In via JTAG
Figure 2
PNX15xx/952x Series system and a simplified block diagram of the PNX15xx/952x
Series processor. The JTAG Interface Module, shown separately in the diagram, may
be a PC add-on card such as PC-1149.1/100F Boundary Scan Controller Board or a
similar module connected to a PC serial or parallel port. The JTAG interface module
is necessary for PNX15xx/952x Series systems that are not plugged into a PC. For
PC-hosted PNX15xx/952x Series systems, the host based TM3260 debugger front-
end can communicate with the target resident debug monitor via the PCI bus.
Enhancements to the standard JTAG functionality include a handshake mechanism
for transferring data to and from a PNX15xx/952x Series processor’s MMIO registers,
support for posting an interrupt, and resetting processor state.
Action
IR shift in SEL_IFULL_IN instruction
While TM_DBG_CTRL2.ifull = 1, scan in SEL_IFULL_IN instruction
DR scan 33 bits of register TM_DBG_IFULL_IN
TOTAL
Figure 2:
shows an overview of the JTAG access path from a host machine to a target
System with JTAG Access
TM3260
CPU
Rev. 4.0 — 03 December 2007
Connector
JTAG
JTAG board
Controller
(such as a PC)
Host Machine
JTAG TAP (TCK, TMS, TDI, TDO)
D$
I$
Internal System Bus
MCU
Peripherals
Connection
Serial or Parallel
Scan Chain connecting possibly
PNX15xx/952x Series
other chips on board
JTAG Interface
Chapter 24: TM3260 Debug
May be a PC plug-in board
Main
(SDRAM)
Memory
© NXP B.V. 2007. All rights reserved.
Module
Number of
TCK Cycles
12
11+
38
61+ cycles
24-752
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