PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 349

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 4:
Clock Gating Logic
3.2.3 BLEN state
3.2.4 PEPED state
3.3 Counter
3.4 Gating Logic
dce_sync
clk_lcd
In the BLEN state, when the lcd_enbl signal is de-asserted, the TFTBKLTON signal is
de-asserted and the counter is loaded with BKLT_DCE_DELAY value. There is no
state transition. When the counter reaches zero with lcd_enbl signal still de-asserted,
the state machine moves to the DCEN state de-asserting the dce signal. During this
transition, the counter is loaded with DCE_PWREN_DELAY value.
If the lcd_enbl signal is asserted in the BLEN state, the TFTBKLTON signal is
asserted and there is no state change.
In the PEPED state, the state machine waits for the counter to reach zero to force the
PWREN_PWREN_DELAY and goes back to the IDLE state. This completes the
power down sequencing. If the lcd_enbl signal is asserted when the counter reaches
zero, a new power up sequencing is started.
The counter used to calculate the delays is a 26-bit down counter. It starts counting
down as soon as it is loaded with a delay value and asserts the cnt_done signal when
the counter reaches zero. It runs on the 27 MHz clock (input PNX15xx/952x Series
crystal).
The control signals from the state machine are in the clk_lcd_tstamp clock domain.
They are first synchronized to the clk_lcd clock domain before using them to gate the
data/control signals from the QVCP. The clk_lcd clock is also gated without any glitch
in the gating logic. The clock gating circuit is shown in
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
clk_lcd_out
Figure
Chapter 10: LCD Controller
4.
© NXP B.V. 2007. All rights reserved.
10-349