PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 759

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
2. Functional Description
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.1.1 IIC Arbitration and Control Logic
1.1 Features
2.1 General Operations
Generation of clock signals on the I
device. Each master generates its own clock signals when transferring data on the
bus. Bus clock signals from a master can only be altered when they are stretched by
a slow-slave device holding down the clock line or by another master when arbitration
occurs.
The main features of the I
The IIC module supports a master/slave I
register, shift timing generation and slave address recognition. It is compliant with the
I
to 400 kHz SCL) are supported.
In the master transmitter mode, the arbitration logic checks that every transmitted
logic ‘1’ actually appears as a logic 1 on the I
overrules a logic ‘1’ and pulls the SDA line low, arbitration is lost and the IIC module
immediately changes from master transmitter to slave receiver. The IIC module will
continue to output clock pulses (on SCL) until transmission of the current serial byte
is complete. Arbitration may also be lost in the master receiver mode. Loss of
arbitration in this mode can only occur while the IIC module is returning a “not
acknowledge” (logic ‘1’) to the bus. Arbitration is lost when another device on the bus
pulls this signal LOW. Since this can occur only at the end of a serial byte, the IIC
module generates no further clock pulses.
The synchronization logic will synchronize the serial clock generator with the clock
pulses on the SCL line from another device. If two or more master devices generate
clock pulses, the “mark” (high level) duration is determined by the device that
generates the shortest marks, and the “space” (low level) duration is determined by
the device that generates the longest spaces.
2
C Bus Specification. Both the I
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Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization, which allows communication between devices with
different bit rates
Using serial clock synchronization as a handshake mechanism to suspend and
resume serial transfer
May be used for test and diagnostic purposes.
Rev. 4.0 — 03 December 2007
2
C bus are as follows:
2
C standard mode (100 kHz SCL) and fast mode (up
2
C bus is always the responsibility of the master
2
C bus interface with an integrated shift
2
C bus. If another device on the bus
PNX15xx/952x Series
Chapter 25: I
© NXP B.V. 2007. All rights reserved.
2
C Interface
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