PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 466

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
2. Functional Description
Table 1: Module signal pins
PNX15XX_PNX952X_SER_N_4
Product data sheet
Signal
clk_fgpo
fgpo_rec_sync
fgpo_buf_sync
fgpo_start
or
fgpo_rec_start
Type
input
input
input
output
Description
From Clock Module. External FGPO clock on VDO_C2 pin is connected to the Clock Module.
FGPO data and control signals are output at each rising edge on clk_fgpo. Use the PNX15xx/
952x Series Clock Module to change clk_fgpo characteristics.
From External PAD.
In external record/message sync mode a programmable transition on this pin will trigger the
output of a record or message after a synchronization delay of 4 FGPO clock cycles. If the
transition occurs before the FGPO has finished the output of a previous record or message,
the transition will be ignored.
From External PAD.
In external buffer sync mode a programmable transition on this pin will start a new buffer after
a synchronization delay of 4 FGPO clock cycles. If the transition occurs before the FGPO has
finished the current buffer, the transition will be ignored.
To External PAD VDO_D[32] via Output Router.
Message Passing Mode:
A positive pulse output on this pin indicates the start of a message. The pulse may be
programmed to occur one clock before or at the same clock with the first valid data sample.
Record Mode:
A positive pulse output on this pin indicates the start of a record. The pulse may be
programmed to occur one clock before or at the same clock with the first valid data sample
or
A positive pulse lasting as long as valid data samples are output.
Rev. 4.0 — 03 December 2007
Chapter 13: FGPO: Fast General Purpose Output
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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