PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 694

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 2: LAN100 Registers
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
Offset 0x07 2FF4
The PowerDown register is used to block all MMIO access except access to the PowerDown register. Setting the bit will
return an error on all register access except for access to the PowerDown register.
In case the LAN100 is in a power-down state because, for example, no PHY is connected, then software should set the
PowerDown bit in the PowerDown register in order to prevent deadlock (for example, due to a speculative read operation of
the CPU).
31
30:0
Offset 0x07 2FFC
The ModuleID register is used to store standard NXP module ID information.
31:16
15:12
11:8
7:0
Symbol
PowerDown
-
ModuleID
MajRev
MinRev
ApertureSize
3.3 Pattern Matching Join Register
Power-down Register (PowerDown)
Module ID Register (ModuleID)
…Continued
The Pattern Matching Join register (PatternMatchJoin) defines the way the outputs of
the four pattern-matching sections are joined together into a single pattern-matching
result. Joining is done by a pyramid architecture in three stages. The first stage
Acces
s
R/W
-
RO
RO
RO
RO
Value
0x3902
0x1
0x1
0
Rev. 4.0 — 03 December 2007
Description
If set, all register access will return a read/write error except
accesses to the PowerDown register.
Unused
Unique 16-bit module identification.
Major design revision number.
Minor design revision number.
Represents the aperture of the software registers in the MMIO
register space. Aperture size is 4 Kb, corresponding to a value 0 in
this field.
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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