PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 244

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 8: Registers Description
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
12
11
10
9
8:7
6
5
4
3
2
1
0
Offset 0x04 0018
31:21
20:0
Offset 0x04 001C
31:21
20:0
Offset 0x04 0020
31:21
20:0
Symbol
xio_wr_post_en
pci2_wr_post_en
pci1_wr_post_en
en_serr_seen
Reserved
en_base10_spec_rd
en_base14_spec_rd
en_base18_spec_rd
disable_subword2_10
disable_subword2_14
disable_subword2_18
en_retry_timer
pci_base1_lo
Reserved
pci_base1_hi
Reserved
pci_base2_lo
Reserved
PCI_Base1_lo
PCI_Base1_hi
PCI_Base2_lo
Acces
s
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
Value
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
0
0
Rev. 4.0 — 03 December 2007
Description
Enable write posting to XIO address range.
Enable write posting to pci_base2 address range.
Enable write posting to pci_base1 address range.
Enable monitoring of the SERR pin.
Read ahead to optimize PCI read latency to base 10.
Read ahead to optimize PCI read latency to base 14.
Read ahead to optimize PCI read latency to base 18.
Disable subword access to/from Base10 aperture.
Disable subword access to/from Base14 aperture.
Disable subword access to/from Base18 aperture.
Enables timer for 16 tic rule enforcer. This bit does not affect access
to the XIO aperture.
For internal address decoding: low bar of first aperture for external
PCI access. This register affects the decode and routing of the bus
controllers. It should not be relied on as stable for 10 clocks after
writing. It is recommended that the PCI_Base1_lo be initialized
before the PCI_Base1_hi to avoid a potentially large segment of
address space being temporarily allocated to PCI space.
For internal address decoding: high bar of first aperture for external
PCI access (up to but not including). This register affects the
decode and routing of the bus controllers. It should not be relied on
as stable for 10 clocks after writing. It is recommended the
PCI_Base1_lo be initialized before the PCI_Base1_hi to avoid a
potentially large segment of address space being temporarily
allocated to PCI space.
For internal address decoding: low bar of second aperture for
external PCI access. This register affects the decode and routing of
the bus controllers. It should not be relied on as stable for 10 clocks
after writing. It is recommended the PCI_Base2_lo be initialized
before the PCI_Base2_hi to avoid a potentially large segment of
address space being temporarily allocated to PCI space. The
PCI_Base2 aperture may be declared as a internal view of PCI IO
space or as PCI memory space. See pci_io register for more
information.
PNX15xx/952x Series
Chapter 7: PCI-XIO Module
© NXP B.V. 2007. All rights reserved.
7-244