PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 260

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 8: Registers Description
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
9
8
7
6
5
4
3
2
1
0
Offset 0x04 0FE4
31:27
26
25
24
23
22
21
20
19
18
17
16
15
14
13:12
11
10
9
8
7
6
5
4
Symbol
pci_err
err_base10_subword
err_base14_subword
err_base18_subword
pci_mstr_parity_err
err_pci_parity
sig_serr
pci_r_mabort
pci_r_tabor
pci_s_tabort
Reserved
en_int_pcii_wr_err
en_int_pcii_rd_err
en_int_xio_wr_err
en_int_xio_rd_err
en_int_pcir_wr_err
en_int_pcir_rd_err
en_int_pwrstate_chg
Reserved
en_int_pci2_wr_err
en_int_pci2_rd_err
en_int_pci1_wr_err
en_int_pci1_rd_err
en_int_pci_xio_ack_don
e
Reserved
en_int_serr_seen
Reserved
en_int_pci_err
en_int_base10_subword R/W
en_int_base14_subword R/W
en_int_base18_subword R/W
en_int_pci_mstr_parity
err
en_int_pci_parity
PCI Interrupt Enable
Acces
s
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R/W
R/W
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 4.0 — 03 December 2007
Description
PCI master transaction attempted when not enabled by config
register
Subword attempt to base10 aperture when restrained to word only
(not used on the PNX15xx/952x Series)
Subword attempt to base14 aperture when restrained to word only
Subword attempt to base18 aperture when restrained to word only
(not used on PNX15xx/952x Series)
PCI master set or observed parity error (PERR)
PCI Detected parity error (PERR)
Signaled system error (SERR)
PCI Received Master Abort
PCI Received Target Abort
PCI Signaled Target Abort
Enable interrupt on PCI DTL initiator write error flag
Enable interrupt on PCI DTL initiator read error flag
Enable interrupt on XIO DTL target write error flag
Enable interrupt on XIO DTL target read error flag
Enable interrupt on mmio register DTL target write error flag
Enable interrupt on mmio register DTL target read error
Enable interrupt on change of power state register
Enable interrupt on PCI2 DTL target write error flag
Enable interrupt on PCI2 DTL target read error flag
Enable interrupt on PCI1 DTL target write error flag
Enable interrupt on PCI1 DTL target read error flag
Enable interrupt on rising edge of xio_ack done
Enable interrupt on SERR observed on PCI bus
Enable interrupt on pci_err flag
Enable interrupt on Subword Attempt to Base10 Error Status
Enable interrupt on Subword Attempt to Base14 Error Status
Enable interrupt on Subword Attempt to Base18 Error Status
Enable interrupt on PCI Master Parity Error
Enable interrupt on PCI Parity Error Status
PNX15xx/952x Series
Chapter 7: PCI-XIO Module
© NXP B.V. 2007. All rights reserved.
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