PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 263

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 9: PCI Configuration Registers
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
30
29
28
27
26:25
24
23
22
21
20
19:10
9
8
7
6
5
4
3
2
1
0
Offset 0x0008
31:8
7:0
Offset 0x000C
31:16
15:8
7:0
Offset 0x0010
Symbol
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
Devsel Timing
Master Data Parity Error R/W
Fast Back-to-Back
Capable
Reserved
66 MHz Capable
Capabilities List
Reserved
Fast back-to-back
enable
SERR enable
Stepping Control
Parity Error Response
VGA Palette Snoop
Memory Write &
Invalidate
Special Cycles
Enable Bus Master
Enable Memory space
IO Space
Class Code
Revision ID
Reserved
Latency Timer
Cache Line Size
Class Code/Revision ID
Latency Timer/Cache Line Size
Base10 Address Register
Acces
s
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R/W
R/W
R
R/W
R
R/W
R
R/W
R/W
R
R/W*
R
R
R/W
R/W
Value
0
0
0
0
01
0
1
0
cfg*
1
0000
0
0
0
0
0
0
0
0
0
0
048000
1
0x0000
0
0
Rev. 4.0 — 03 December 2007
Description
This bit is set whenever the device asserts SERR. Write 1 to clear.
Set by the PCI master when its transaction is terminated with a
master abort. Write 1 to clear.
Set by the PCI master when its transaction is terminated with a
target abort. Write 1 to clear.
Set by the PCI target when it terminates a transaction with a target
abort. Write 1 to clear.
The PCI target uses medium DEVSEL timing.
Set by the PCI master when PERR is observed.
The PCI supports fast back-to-back transactions.
0 = 33 MHz PCI (The PNX15xx/952x Series is 33 MHz).
*Value determined by pci_setup register.
Indicates a new Capabilities linked list is available at offset 40h.
Enable fast back-to-back transactions for PCI master.
Enable SERR to report system errors.
Address stepping is not supported.
0 = No parity error response
1 = Enable parity error response.
VGA is not supported.
Enable use of memory write and invalidate.
Special cycles are not supported.
Enable the PCI bus master.
Enable all memory apertures.
The PCI module does not respond to IO transactions.
The PNX15xx/952x Series is defined as a multimedia device.
*The boot loader may change the class code to an alternate value if
done before writing to the pci_setup register.
Revision ID. Will initially be assigned to 0. Revision ID must not be
synthesized. It will need to be changed with revised silicon, whether
for bug fixes or enhancements.
Note: BIST is not implemented. Header is 0.
Latency Timer
Cache Line Size
PNX15xx/952x Series
Chapter 7: PCI-XIO Module
© NXP B.V. 2007. All rights reserved.
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