PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 250
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PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
Specifications of PNX1500E
Lead Free Status / Rohs Status
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Volume 1 of 1
Table 8: Registers Description
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
7:5
4
3:0
Offset 0x04 0810
31:2
1
0
Offset 0x04 0814
This register sets up the profile of the XIO select 0 line. All times are in reference to PCI clocks.
31:25
24
23
22
21:18
17:14
13:9
8:5
Symbol
max_burst_size
init_dma
cmd_type
Reserved
xio_ack
Reserved
Reserved
misc_ctrl
en_16bit_xio
sel0_use_ack
sel0_we_hi
sel0_we_lo
sel0_wait
sel0_offset
XIO Control Register
XIO Sel0 Profile
Acces
s
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 4.0 — 03 December 2007
Description
PCI transaction will be split into multiple transactions. Max size:
000 = 8 data phase
001 = 16 data phase
010 = 32 data phase
011 = 64 data phase
100 = 128 data phase
101 = 256 data phase
110 = 512 data phase
111 = No restriction in transfer length
Initiate DMA transaction. This bit is cleared by the DMA engine
when it begins its operation.
Command to be used for DMA. This field is restricted to memory
type or IO type commands as defined in the PCI 2.2 spec.
Live XIO_ACK status bit.
68360: 1 synchronous DSACK; 0 asynchronous DSACK.
NOR: Not used
NAND: Not used
IDE: Not used
0 = 8 bit XIO device
1 = 16 bit XIO device
0 = Fixed wait state
1 = Wait for ACK
Not used for IDE.
68360: DS time high.
NOR: WN time high
NAND: REN profile, [19:18] low time; [21:20] high time
IDE: DIOR and DIOW high time
68360: Not used.
NOR: WN time low
NAND: WEN profile, [15:14] low time; [17:16] high time
IDE: DIOR and DIOW low time
68360: DS time low if using fixed timing.
NOR: OEN time low if not using ACK.
NAND: Delay between address and data phase if not using ACK,
delay until monitoring ACK.
IDE: Not used.
Starting address offset from start address of XIO aperture, in 8M
increments. This field must be naturally aligned with the size of the
profile.
PNX15xx/952x Series
Chapter 7: PCI-XIO Module
© NXP B.V. 2007. All rights reserved.
7-250
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