PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 767

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 3: IIC Registers
PNX15XX_PNX952X_SER_N_4
Product data sheet
Offset 0x04 5004
31:8
7:0
Bit
Symbol
Unused
DAT
I2C DATA REGISTER
When the STOP condition is detected on the bus, the IIC module hardware clears the
STO flag. In a slave mode, the STO flag may be set to recover from an error
condition. In this case, no STOP condition is transmitted to the I
IIC module hardware behaves as if a STOP condition has been received and
switches to the defined “not addressed” slave receiver mode. The STO flag is
automatically cleared by the hardware.
If the STA and STO bits are both set, the STOP condition is transmitted to the I
if IIC module is in master mode. In slave mode, the IIC module generates an internal
STOP condition, which is not transmitted. It then transmits a START condition.
When the STO bit is reset, no STOP condition will be generated.
There is also no interrupt generated for detection of a STOP condition which was
created by the IIC. (The IIC needs to be in master mode to do this). And there is no
status code for this condition in the IIC STATUS register.
Bits [2:0]: CR
For details, see Bits[2:0] in Offset
Bit [7:0]: DAT
DAT contains a byte of serial data to be transmitted or a byte which has just been
received. This special function register can be read from or written to while it is not in
the process of shifting a byte. This occurs when IIC module is in a defined state. Data
in DAT is always shifted from right to left: the first bit to be transmitted is the MSB (bit
7), and after a byte has been received, the first bit of received data is located at the
MSB of DAT. While data is being shifted out, data on the bus is simultaneously being
shifted in; DAT always contains the last data byte present on the bus. Thus, in the
event of lost arbitration, the transition from master transmitter to slave receiver is
made with the correct data in DAT. Reset initializes DAT to 0x00.
A logic ‘1’ in DAT corresponds to a high level on the I
corresponds to a low level on the bus. Serial data shifts through DAT from right to left.
DAT and the ACK flag form a 9-bit shift register which shifts in or shifts out 8 bits,
followed by an acknowledge bit. The ACK flag is controlled by the IIC module
hardware and cannot be accessed by the CPU. Serial data is shifted through the ACK
flag into DAT on the rising edges of clock pulses on the SCL line. When a byte has
been shifted into DAT, the serial data is available in DAT, and the acknowledge bit is
returned by the control logic during the 9th clock pulse. Serial data is shifted out from
DAT via a buffer on the falling edges of clock pulses on the SCL line.
Acces
s
R/W
Value
-
0
Rev. 4.0 — 03 December 2007
Description
Ignore upon read. Write as zeroes.
Write byte data to be transmitted on the I2C bus.
Read byte data has been received from the I2C bus.
0x04 5000 I2C CONTROL
PNX15xx/952x Series
2
C bus, and a logic ‘0’
Chapter 25: I
of the register table.
2
C bus. However, the
© NXP B.V. 2007. All rights reserved.
2
C Interface
2
C bus
25-767