PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 646

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 32: EngineConfig
Table 33: HostFIFOStatus
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
2
1
0
Bit
Offset 0x04 F80C
31:6
5:0
Symbol
BSM
BSI
Reserved
Symbol
Reserved
Level[5:0]
HostFIFOStatus
This register is used to configure specific drawing engine features and to enable the
interrupt request signal.
BSI (bit 1) and BSM (bit 2) toggle byte and word swapping. Certain registers which
contain byte- or word-oriented data but which must be manipulated as
to be byte- or word-swapped when written on big-endian architectures. These include
HostData, PatRamMono and PatRamColor. The drawing engine automatically
determines whether swapping is necessary based on the global “endian” flag.
The bottom byte of this register should not be altered while drawing commands are in
progress.
This register is used to provide software with a method of determining the number of
available entries in the Host FIFO.
There are 32 FIFO locations in the Host FIFO. If this register is read as 0, it indicates
there are no available FIFO locations available for writing. A write to the Host FIFO
while the FIFO is full (or almost full) will result in wait states on the PI bus.
If this register is read as 0x20, it indicates that all 32 entries are available for writing.
A software driver can read this register and subsequently write the corresponding
number of
Series from generating PCI retries since a write will not occur when the Host FIFO is
full.
Acces
s
R/W
R/W
Acces
s
R
DWORD
Value
0
0
Value
0x20
Rev. 4.0 — 03 December 2007
s of data to the Host FIFO. This will prevent the PNX15xx/952x
Description
BSI (bit 1) and BSM (bit 2) toggle byte and word swapping. Setting
BSI to 1 reverses the sense of the global endian bit for data read
from the host data input port, so that data are swapped when written
when they normally would not be, and vice versa. This bit affects
host BLT data, pattern loading. It is intended for debugging and
should be set to 0 for normal operation.
BSI (bit 1) and BSM (bit 2) toggle byte and word swapping. Setting
BSM to 1 reverses the sense of the global endian bit for data being
read and written to the memory port. It is intended for debugging
and should be set to 0 for normal operation.
Description
Used to provide software with a method of determining the number
of available entries in the Host FIFO.
PNX15xx/952x Series
Chapter 20: 2D Drawing Engine
© NXP B.V. 2007. All rights reserved.
DWORDS
need
20-646