PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 159
PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
Specifications of PNX1500E
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Table 2: Current Adjustment Values Based on N
Table 3: PLL Settings
PNX15XX_PNX952X_SER_N_4
Product data sheet
30-37 38-46 47-54 55-63 64-72 73-82 83-89 90-97 98-107 108-116 117-125 126-133 134-142 143-151 152-160 161-180
0xF
F
133.07 MHz 266.14 MHz 27 MHz CRYSTAL
181.29 MHz 362.57 MHz 27 MHz CRYSTAL
266.63 MHz 533.25 MHz 27 MHz CRYSTAL
300.38 MHz 600.75 MHz 27 MHz CRYSTAL
166.5 MHz
199.8 MHz
240.3 MHz
out
27 MHz
54 MHz
65 MHz
81 MHz
0xE
0xD
F
399.6 MHz
480.6 MHz
vco
216 MHz
432 MHz
520 MHz
324 MHz
333 MHz
0xC
0xB
F
27 MHz CRYSTAL
27 MHz CRYSTAL
27 MHz CRYSTAL
in
27.012987 MHz
PLL Settings
An easy way to determine the N over M ratio is to meet the PLL limitations seen
above and solve the following equation:
PLL Setting Examples
Table 1
PLL2 (for the DDR) has the P parameter wired to ‘1’.
---- -
M
N
•
•
0xA
=
27 MHz
27 MHz
27 MHz
Run the VCO as high as possible, therefore for low output frequencies chose high
P values
Ensure
DDS1
DDS1
DDS1
DDS1
F
---------- -
F
vco
in
presents some other typical examples to set the PLL N, M and P parameters.
0x9
30 N 180
0x8
Rev. 4.0 — 03 December 2007
M
4
3
4
3
7
3
7
5
5
4
4
0x7
and track N with the following current adjustment values:
N
0x4D
0x5E
0x4A
0x4F
0x20
0x30
0x24
0x45
0x25
0x59
0x59
0x6
P
n/a
n/a
n/a
n/a
3
3
3
2
1
1
1
0x5
ADJ Destination Examples
0xF QVCP from DDS1
0xD QVCP from DDS1
0xA QVCP from DDS1
0xF QVCP from DDS1
0xB DDR266, i.e. <= 133.333333 MHz MM_CK
0xF DDR333, i.e. <= 166.666666 MHz MM_CK
0xA DDR400, i.e. <= 200.000000 MHz MM_CK
0xA 266 MHz TM3260, i.e. PNX1501 or PNX1520
0x8 DDR366, i.e. <= 181.818181 MHz MM_CK
0x9 240 MHz TM3260, i.e. PNX1500
0x9 300 MHz TM3260, i.e. PNX1502
50% duty cycle recommended
50% duty cycle recommended
50% duty cycle recommended
50% duty cycle recommended
0x4
PNX15xx/952x Series
0x3
Chapter 5: The Clock Module
0x2
© NXP B.V. 2007. All rights reserved.
0x1
0x0
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