PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 519

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
3. Operation
PNX15XX_PNX952X_SER_N_4
Product data sheet
3.1.1 Sample Clock Generator
3.1 Clock Programming
If an HBE error occurs, the last valid sample or sample pair is repeated until the Audio
Out hardware receives enough data to generate a new serial data frame from the
DMA interface adapter.
The sample clock generator is programmable to support various sample frequencies.
Figure 6
wave Direct Digital Synthesizer (DDS) drives the clock system. This DDS is external
to the Audio Out block.
Using the DDS as a clock source allows software to control the coarse and fine clock
rate so that complex forms of synchronization can be implemented without external
hardware. Examples include locking the audio to a broadcast clock, or locking it to an
SPDIF input without changing the system's hardware.
The DDS output is always sent to the OSCLK output pin. This output is intended to be
used as the 256 Fs or 384 Fs system clock source for oversampling D/A converters.
Software may change the oversampling clock frequency dynamically (via the DDS
controls) to adjust the outgoing audio sample rate. In ATSC transport stream
decoding, this is the method used by which the system software locks the audio
output sample rate to the original program provider sample rate.
OSCLK
Figure 6:
SD[0]
SD[1]
SD[2]
SD[3]
SCK
(e.g. 64 x Fs)
WS
(e.g. 256 x Fs)
illustrates the different clock capabilities of the Audio Out unit. A square
Audio Out Clock System and I/O Interface
Rev. 4.0 — 03 December 2007
Parallel to Serial
Converter
div N+1
div N+1
SER_MASTER
8
7
16 or 32
16 or 32
32
WSDIV
SCKDIV
Audio Out domain
RIGHT sample
AO_CC[31:0]
LEFT sample
PNX15xx/952x Series
0
0
Chapter 15: Audio Output
27 MHz x 64
© NXP B.V. 2007. All rights reserved.
Square Wave
DDS from
Clocks Module
DDS
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