PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 797

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
4. Universal Converter
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 12: Packed 10-bit YUV 4:2:2 Format
Address a0+4
31
31
Address a0
31
Address a0 + 8
Address a0 + 12
31
Py
(a)
alpha
alpha
alpha
alpha
3.5.3 Packed 10-bit YUV 4:2:2 format
Y linepitch
V1
Y3
Y6
U3
The packed 10-bit YUV 4:2:2 format is generated by an external device and stored in
the PNX15xx/952x Series memory through the Tunnel interface. QVCP supports the
packed 10 bit YUV 4:2:2 format, as shown in
Register view after 32-bit load (applicable to both endianness)
The MBS input stage contains a universal pixel format converter that can convert any
packed 16 or 32-bit pixel RGB format to an 8-bit alpha, R, G and B value for internal
processing. This conversion can be done in combination with any MBS operation,
particularly anti-flicker filtering.
The conversion is done by specifying the following:
•
•
•
the width (16 or 32 bits) of a unit (this designates endian mode handling)
the position (bit 31..0) within the unit for each of the alpha, R,G and B fields
the width (1..8 bit) of each of the alpha, R,G and B fields
Note: Each word(4-Byte) is swapped for Big-endian and stored in memory
U1-V1 Y2-Y3 V2-U3
U1-V1 Y2-Y3 V2-U3
U1-V1 Y2-Y3 V2-U3
4 bytes
a
G
G
G
G
a+4
20
20
20
20
19
19
19
19
Rev. 4.0 — 03 December 2007
a+8
. . . .
. . . .
. . . .
2W(4/3) bytes
. . . .
. . . .
. . . .
Y1
U2
V3
Y4
G
G
G
G
10
10
10
10
1st line
2nd line
last line
Figure
9
9
9
9
PNX15xx/952x Series
12.
Chapter 28: Pixel Formats
H lines
U1
Y2
Y5
V2
© NXP B.V. 2007. All rights reserved.
10-bit Y,U,V
0
0
0
28-797