PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 111

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.2 The CPU View
Remark: Partial 32-bit load or stores from a PCI master to an MMIO register is not
supported. Therefore byte of 16-bit half-word accesses are not supported.
The TM3260 CPU supports three different apertures:
Remark: To ensure backward compatibility with future devices, writes to any
undefined or reserved MMIO bit should be ‘0’, and reads should be ignored. This rules
applies to ALL the modules of PNX15xx/952x Series.
TM3260 CPU accesses the three apertures using regular load/store operations.
Some internal logic in the data cache unit surveys the load/store addresses and
routes the request to the appropriate internal PNX15xx/952x Series registers (this
includes the registers belonging to TM3260) if the address falls into the MMIO
aperture. If the load/store address falls into the DRAM aperture the load/store request
is routed to the data cache and eventually the main memory. Finally if the load/store
address falls into the APERT1 aperture, the request is send to the PCI bus (if it maps
to an XIO device or a PCI internal aperture, see the following
Figure 2
PNX15xx/952x Series system. The apertures can be placed in any order with respect
to each other.
PNX15xx/952x Series allows a host CPU to prevent TM3260 to change its own
aperture registers. This can be obtained by flipping
TM32_CONTROL.TM32_APERT_MODIFIABLE to ‘1’
locations are defined as follows:
Remark: If the value 0x0000,0000 is stored into TM32_DRAM_HI, this value is
understood as 0x1,0000,0000.
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the MMIO aperture, used to access all the internal PNX15xx/952x Series
registers. See
the DRAM aperture, used to access the main memory of PNX15xx/952x Series
which contains the instruction and the data for TM3260 and data used by other
PCI masters.
the APERT1 aperture, used by TM3260 to access low speed slave devices like
Flash memories or IDE disk drives that are located in the XIO aperture or any
other PCI slave.
The MMIO aperture is starting at the address contained in the BASE_14 MMIO
register. The register is located and owned by the PCI module. It is equivalent to
the BASE_14 PCI Configuration space register. This is different with respect to
PNX1300 Series or PNX1300 Series where an MMIO_BASE MMIO register was
available.
The DRAM aperture is starting at the address contained in the TM32_DRAM_LO
MMIO register and finishes at TM32_DRAM_HI - 1.
The APERT1 aperture is starting at the address contained in the
TM32_APERT1_LO MMIO register and finishes at TM32_APERT1_HI - 1.
presents the memory map seen by the TM3260 and the remaining of the
Rev. 4.0 — 03 December 2007
Section 11. on page 3-139
Chapter 3: System On Chip Resources
for offset allocation per module.
PNX15xx/952x Series
(Section
Section
2.4.1). The aperture
© NXP B.V. 2007. All rights reserved.
2.3).
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