PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 703

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
5.2.1 Descriptor FIFOs
5.2.2 Ownership of Descriptors
5.2 Direct Memory Access
The MMIO interface will return a read error if an MMIO read operation accesses a
write-only register; likewise a write error is returned if an MMIO write operation
accesses to the read-only register. An MMIO read or write error will be returned on
MMIO read or write accesses to reserved registers.
If the PowerDown bit of the PowerDown register is set, all MMIO read and write
accesses will return a read or write error except for accesses to the PowerDown
register.
The LAN100 includes three high-performance DMA managers. The DMA managers
make it possible to transfer packets directly to and from memory with little support
from the processor, and without the need to trigger an interrupt for each packet.
The DMA managers work with FIFOs of packet descriptor structures and status
structures that are stored in host memory. The descriptor structures and status
structures act as an interface between the Ethernet hardware module and the device
driver software. There is one descriptor FIFO for receive packets and there are two
descriptor FIFOs for transmit packets, one for real-time transmit traffic, and one for
non-real-time transmit traffic. By separating the areas in memory where the device
driver and Ethernet module each carry out write operations, it is easy to maintain
memory coherency and to make the descriptors cache safe , so that cache memory
can be used to store descriptors. Using caching and buffering for packet descriptors,
the memory traffic and memory bandwidth utilization of descriptors can be kept small.
This makes the descriptor format scalable to high speeds, including gigabit ethernet.
Each packet descriptor structure contains a pointer to a data buffer containing a
packet or packet fragment, a control word, a status word, and a time stamp for
real-time transmit.
The software driver determines the memory locations of the descriptor and status
arrays and writes their base addresses in the TxDescriptor, TxRtDescriptor,
RxDescriptor and TxStatus, TxRtStatus, RxStatus registers. The number of
descriptor structures and status structures in each array should be written in the
TxDescriptorNumber, TxRtDescriptorNumber and RxDescriptorNumber registers.
The number of descriptor structures in an array should correspond to the number of
status structures in the associated status array.
Descriptor structure arrays must be aligned on a 4-byte (32-bit) address boundary;
status structure arrays must be aligned on an 8-byte (64-bit) address boundary.
Both device driver software and Ethernet hardware can read and write the descriptor
FIFOs simultaneously to produce and consume descriptors. A descriptor is either
owned by the device driver or it is owned by the Ethernet hardware. Only the owner of
a descriptor reads or writes its value. Typically, the sequence of use and ownership of
descriptor structures and status structures is as follows:
•
A descriptor structure is owned and set up by the device driver
Rev. 4.0 — 03 December 2007
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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