PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 168

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 6:
(external clock)
Clock Detection Circuit
2.9 Clock Detection
en
counter
Toggle
Flop
The GPIO interrupt comes from the GPIO block and is the “OR” of all the FIFO and
timestamp registers. This way a GPIO pin can be monitored and when an event
occurs the interrupt to the processor awakes the system. Bit ‘0’ of the
CLK_WAKEUP_CTL enables the GPIO interrupt.
The external signal is the dedicated GPIO pin 15. This signal must be active for at
least one xtal_clk clock period. It is expected that this signal will stay active until the
CPU responds which will be several xtal clock periods. Bit ‘1’ of the
CLK_WAKEUP_CTL enables the external interrupt. GPIO[15] must be low when
entering in power down mode since the wake-up procedure is started when the
GPIO[15] pin is set to high for at least one xtal_clk clock cycle.
Clock detection is required in the case of an external clock being removed or
disconnected e.g if the video cable to the set top box is suddenly removed and an
external video clock thereby stopped. this type of event is detected by the Clock
module. Also the Clock module can detect when the cable is re-connected and a
clock is present again.
These events are flagged by an interrupt which is routed to the TM3260.
The clock detection will be done on the following clocks inputs to PNX15xx/952x
Series:
Clock detection is done based on a 5-bit counter running at the crystal clock
frequency. The implementation detects clocks between 1 MHz and 200 MHz. It will
take up to 2 s from when the clock is removed until the interrupt condition is
generated. A block diagram of the clock detection circuit is shown in
xtal_clk
•
•
•
•
•
VDI_CLK1 (clk_vip)
AI_SCK
AO_SCK
VDI_CLK2 (clk_fgpi)
VDO_CLK2 (clk_fgpo)
32
xtal_clk
Rev. 4.0 — 03 December 2007
en
xtal_clk
comp
clock_present
detect
edge
PNX15xx/952x Series
Chapter 5: The Clock Module
pls2lvl
PIO
INT
© NXP B.V. 2007. All rights reserved.
Figure
intrpt_clk
6.
5-168