PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 511

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 2: Operating Modes and Memory Formats
PNX15XX_PNX952X_SER_N_4
Product data sheet
NR_CHAN
00
00
01
01
10
10
11
11
Figure 2:
NR_CHAN=10
16 bit, stereo,
NR_CHAN=00
16 bit, stereo,
32 bit, stereo,
NR_CHAN=00
Examples of Audio Out Memory DMA Formats
SD[0].left
SD[0].left
MODE
mono
stereo
mono
stereo
mono
stereo
mono
stereo
adr
adr
2.2.1 Endian Control
2.2 Memory Data Formats
SD[0].left
n
n
adr
SD[0].right
SD[0].right
The Audio Out unit autonomously obtains samples from memory in 16 or 32-bit per
sample memory formats, as shown in
from increasing memory address locations.
The Audio Out implements a double buffering scheme in memory to ensure that there
are always samples available to transmit, even if the system controller is highly
loaded and slow to respond to interrupts. The software assigns two equal size buffers
in memory by writing 2 base addresses and a sample size to the corresponding
MMIO registers described in
Prior to output transmission, if SIGN_CONVERT = 1, the MSB of the memory data is
inverted. This allows the use of external two’s complement 16-bit D/A converters to
generate audio from 16-bit unsigned samples. This MSB inversion also applies to the
‘0’ values transmitted to non-active output channels.
Note that the Audio Out hardware does not support A-law or m-law data formats. If
such formats are desired, the system DSP processor should be used to convert from
A-law or m-law data to 16-bit linear data.
Audio Out expects data to be supplied in little endian byte ordering mode. In little
endian byte ordering mode, the least significant byte has the lowest memory address.
•
adr+2
adr+2
n
Destination of Successive Samples
SD[0].left
SD[0].left, SD[0].right
SD[0].left, SD[1].left
SD[0].left, SD[0].right, SD[1].left, SD[1].right
SD[0].left, SD[1].left, SD[2].left
SD[0].left, SD[0].right, SD[1].left, SD[1].right, SD[2].left, SD[2].right
SD[0].left, SD[1].left, SD[2].left, SD[3].left
SD[0].left, SD[0].right, SD[1].left, SD[1].right, SD[2].left, SD[2].right, SD[3].left, SD[3].right.
Complex serial frames of up to 512 bits/frame
n+1
n
SD[0].left
SD[1].left
adr+4
adr+4
Rev. 4.0 — 03 December 2007
SD[0].right
n+1
n
adr+4
SD[0].right
SD[1].right
n
adr+6
adr+6
Section 4. on page
n+1
n
SD[0].left
SD[2].left
Figure
adr+8
adr+8
SD[0].left
n+2
adr+8
n
2. Successive samples are always read
SD[0].right
PNX15xx/952x Series
SD[2].right
15-522.
n+1
adr+10
adr+10
n+2
n
Chapter 15: Audio Output
SD[0].left
SD[0].left
adr+12
adr+12
SD[0].right
© NXP B.V. 2007. All rights reserved.
adr+12
n+3
n+1
SD[0].right
SD[0].right
adr+14
adr+14
n+1
15-511
n+3
n+1