PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 283

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.5 The GPIO Clock Pins
2.6 GPIO Interrupts
GPIO[14:12,6:4] pins can be assigned to drive a clock generated from the clock
module. These are clocks generated by DDS clock generators.
mapping between DDS clocks and the GPIO pins through which they are routed to.
The clocks on pins 4, 5 and 6 can be used as clock sources for the FIFO queues. In
this case the clocks are first routed to the pins, GPIO[4], GPIO[5] and GPIO[6], and
then brought back inside the chip as any other external clock source would be. To use
this feature the GPIO_EV register should be programmed in the following way:
GPIO_EV.EN_CLOCK_SEL = enabled, i.e. set to binary code 01 or 11
GPIO_EV.EN_DDS_SOURCE = enabled, i.e. set to ‘1’.
GPIO_EV.CLOCK_SEL = select between pins 4, 5 or 6
The clocks are selectable individually.
The clocks on pins 12, 13 and 14 are only routed to the PNX15xx/952x Series pins
and can be used as clock sources for some external devices, or loop back on the
system board to GPIO[3:0]. They are not directly used as internal clock sources for
the FIFO queues. In order to route the clocks on these GPIO[14:12] pins, the
DDS_OUT_SEL MMIO register should be programmed appropriately.
Table 4: GPIO clock sources
Each operating FIFO queue can generate 4 types of interrupts:
Each timestamp unit has 2 types of interrupts:
Each FIFO queue has its own interrupt line to the TM3260 CPU, see
page 3-120
GPIO[x] pin
14
13
12
6
5
4
•
•
•
•
•
•
BUF1_READY: DMA buffer 1 ready for reading or writing
BUF2_READY: DMA buffer 2 ready for reading or writing
FIFO_OE: DMA buffer overrun error
INT_OE: Internal buffering overrun error.
DATA_VALID: TSU has data ready to be read
INT_OE: Internal buffering overrun error
for SOURCE number allocation.
Rev. 4.0 — 03 December 2007
Possible Clock Source
DDS0 or DDS2 (The selection is made in the clock module)
DDS5 or DDS1 (The selection is made in the clock module)
DDS6
DDS6
DDS7
DDS8
Chapter 8: General Purpose Input Output Pins
PNX15xx/952x Series
Table 4
© NXP B.V. 2007. All rights reserved.
Table 5 on
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