PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 456

PNX1500E

Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PNX1500E

Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PNX1500E
Manufacturer:
NORTEL
Quantity:
1 000
NXP Semiconductors
Volume 1 of 1
Table 10: Video Input Processor (VIP) 1 Registers
PNX15XX_PNX952X_SER_N_4
Product data sheet
11:10
9:8
7:0
Offset 0x10 6304
31:27
26:16
15:11
10:0
Video Output Address Generation Control Registers
Offset 0x10 6340
31:28
27: 3
2:0
Offset 0x10 6344
31:15
14: 3
2:0
Offset 0x10 6348
Bit
Symbol
PSU_DITHER
PSU_ALPHA
PSU_OPFMT
reserved
PSU_LSIZE
reserved
PSU_LCOUNT
reserved
PSU_BASE1
PSU_OFFSET1
Unused
PSU_PITCH1
Unused
Target Window Size
Target Base Address #1
Target Line Pitch #1
Target Base Address #2
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
-
0
-
0
-
-
-
Value
Rev. 4.0 — 03 December 2007
…Continued
Description
Output format dither mode
00: no dithering
01: error dispersion (never reset pattern)
10: error dispersion (reset pattern at first capture enable)
11: error dispersion (reset pattern every field)
Output format alpha mode
00 = no alpha (alpha byte not written)
01 = alpha byte written, value from CKEY_ALPHA (offset 284)
10 = reserved
11 = reserved
setting 00 is ignored if size of alpha component is less than 8 bits
Output formats
08 (hex) = YUV 4:2:2, semi-planar
0B (hex) = YUV 4:2:2, planar
0F (hex) = RGB or YUV 4:4:4, planar
A9 (hex) = compressed 4/4/4 + (4 bit alpha)
AA (hex) = compressed 4/5/3 + (4 bit alpha)
AD (hex) = compressed 5/6/5
A0 (hex) = packed YUY2 4:2:2
A1 (hex) = packed UYVY 4:2:2
E2 (hex) = YUV or RGB 4:4:4 + (8 bit alpha)
E3 (hex) = VYU 4:4:4 + (8 bit alpha)
Line size
Used for horizontal cropping after scaling
0 = cropping disabled
1 = one pixel
Line count
Used for vertical cropping after scaling
0 = cropping disabled
1 = one line
Base address DMA #1
used depending on PSU_BAMODE setting
Base address byte offset plane 1
bits define pixel offset within multi pixel 64 bit words
(e.g. a 16bit pixel can be placed on any 16 bit boundary)
Line pitch DMA #1, signed value (two’s complement)
used for all packed formats and for plane 1
Chapter 12: Video Input Processor
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
12-456

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