PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 431

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 3:
Digital Video Input Port Timing Relationships in HD Mode
Channel B
Channel A
2.2.2 Input Timing
DV_VALID
2.3 Test Pattern Generator
Y_BuS
UV_BUS
CLK
SD Video Mode
The interleaved data (YUV) is captured from the dv_data[9:0] input, also called
Channel A. The dv_d_data, also called Channel B, is not used in the SD mode.
HD Mode
The Y data is expected on dv_d_data[9:0] (Channel B) and U/V data is expected on
dv_data[9:0] (Channel A).
RAW MODE
In RAW mode the data can be captured from Channel A or B.
A separate signal, dv_valid, is provided to validate all incoming data. The relationship
between dv_valid and data, with reference to clock, is shown in
The Test Pattern Generator produces a video stream with a pixel frequency of half the
VIP input clock e.g., the 27 MHz encoder clock by programming the clock selection
block accordingly.
The sync generation is NTSC-like, with 525 lines per frame and 858 pixels per line.
The active video range is 720x462 bordered by a white frame.
The test pattern is shown in
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–
–
–
–
–
–
–
U0
Y0
A white 2-pixel wide frame—size 720x462
A color bar—white 100%, yellow 75%, cyan 75%, green 75%, magenta 75%,
red 75%, blue 75%, and black 0%.
A grey ramp—full value range 0–255
A vertical multiburst
A horizontal multiburst—first rectangle solid in odd, second solid in even field
Vertical lines
A moving cursor
Test pattern
Rev. 4.0 — 03 December 2007
Y1
V0
U1
Y2
Figure
4, and contains the following elements:
Y3
V1
Chapter 12: Video Input Processor
PNX15xx/952x Series
U2
Y4
Figure
© NXP B.V. 2007. All rights reserved.
Y5
V2
3.
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