PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 476

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
4. Register Descriptions
Table 2: Register Summary
Table 3: Fast general purpose output (FGPO)
PNX15XX_PNX952X_SER_N_4
Product data sheet
Offset
0x07,1000
0x07,1004
0x07,1008
0x07,100C
0x07,1010
0x07,1014
0x07,1018
0x07,101C
0x07,1020
0x07,1024
0x07,1028
0x07,102C
0x07,1030
0x07,1034
0x07,1038 -
0x07,1FDC
0x07,1FE0
0x07,1FE4
0x07,1FE8
0x07,1FEC
0x07,1FF0
0x07,1FF4
0x07,1FF8
0x07,1FFC
Bit
FPGO Registers
Offset 0x07,1000
31:22
21
Symbol
Reserved
POLARITY_IN
Name
FGPO_CTL
FGPO_BASE1
FGPO_BASE2
FGPO_SIZE
FGPO_REC_SIZE
FGPO_STRIDE
FGPO_NREC1
FGPO_NREC2
FGPO_THRESH1
FGPO_THRESH2
FGPO_REC_GAP
FGPO_BUF_GAP
FGPO_TIME1
FGPO_TIME2
reserved
FGPO_IR_STATUS
FGPO_IR_ENA
FGPO_IR_CLR
FGPO_IR_SET
FGPO_SOFT_RST
FGPO_IF_DIS
FGPO_MOD_ID_EX
T
FGPO_MOD_ID
4.1 Mode Register Setup
FGPO_CTL
Acces
s
R
R/W
Clock
Domain
fgpo
mmio
mmio
fgpo
fgpo
fgpo
mmio
mmio
fgpo
fgpo
fgpo
fgpo
fgpo
fgpo
n/a
mmio
mmio
mmio
mmio
mmio
mmio
mmio
mmio
Value
0
0
Rev. 4.0 — 03 December 2007
Description
Controls operational mode and enables/disables DMA transfers
Starting address for first buffer
Starting address for second buffer
Number of records/messages per buffer
Size of record/message in samples
Address stride between records/messages
Number of records/messages transferred from buffer 1
Number of records/messages transferred from buffer 2
Interrupt Threshold for Buffer 1
Interrupt Threshold for Buffer 2
Delay between records/messages
Delay between buffers
Timestamp when buffer 1 was finished
Timestamp when buffer 2 was finished
Module Interrupt Status
Module Interrupt Enables
Module Interrupt Clear (Interrupt Acknowledge)
Module Interrupt Set (Debug)
Module Software Reset
Module Interface Disable
Module ID Extension
Module ID
Description
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Determines clk_fgpo clock sampling edge for fgpo_rec_sync and
fgpo_buf_sync inputs:
0 = use same active edge as for outputs
1 = use alternate active edge as for outputs
Chapter 13: FGPO: Fast General Purpose Output
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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