PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 20
PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
Specifications of PNX1500E
Lead Free Status / Rohs Status
Not Compliant
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Volume 1 of 1
Chapter 4: Reset
Table 1:
Chapter 5: The Clock Module
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Chapter 6: Boot Module
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Chapter 7: PCI-XIO Module
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Chapter 8: General Purpose Input Output Pins
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Chapter 9: DDR Controller
Table 1:
Table 2:
PNX15XX_PNX952X_SER_N_4
Product data sheet
RESET Module
PNX15xx/952x Series Module and Bus Clocks
154
Current Adjustment Values Based on N
PLL Settings
PLL Characteristics
Internal Clock Dividers
DDS and PLL Clock Assignment
The Boot Modes
The Boot Commands
Default DDR SDRAM Timing Parameters
CAS Latency Related DDR SDRAM Timing
Parameters
PCI Setup and PCI Command register
Content
Supported PCI Commands
XIO Pin Multiplexing
Recommended Settings for NAND
GPXIO Address Configuration
IDE Timing
GPIO Pin List
GPIO Mode Select
Settings for MASK[xx] and IOD[xx] Bits
GPIO clock sources
Example of IR Characteristics
Register Summary
GPIO Mode Control Registers
GPIO Data Control
Readable Internal PNX1500 Signals
Sampling and Pattern Generation Control
Registers for the FIFO Queues
Signal and Event Monitoring Control Registers
for the Timestamp Units
CPU Preemption Field
32-Byte Interleaving, 256 Columns
210
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
209
. . . . . . . . . . . . . . . . . . . . . . . . . . 159
. . . . . . . . . . . . . . . . . . . . . . . . . 269
. . . . . . . . . . . . . . . . . . . . . . . . 149
. . . . . . . . . . . . . . . . . . . . . . . 204
. . . . . . . . . . . . . . . . . . . . . 270
. . . . . . . . . . . . . . . . . . . . . 287
. . . . . . . . . . . . . . . . . . . . . 292
. . . . . . . . . . . . . . . . . . . . 160
. . . . . . . . . . . . . . . . . . . . 283
. . . . . . . . . . . . . . . . . . . 208
. . . . . . . . . . . . . . . . . . . 222
. . . . . . . . . . . . . . . . . . 320
. . . . . . . . . . . . . . . . . 160
300
. . . . . . . . . . . . . 221
. . . . . . . . . . . 234
. . . . . . . . . . . 284
. . . . . . . . . . . 290
293
. . . . . . . . . 161
Rev. 4.0 — 03 December 2007
. . . . . . . 224
. . . . . . . 323
. . . . . 292
. . . 271
. . 159
. 209
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 6:
Table 7:
Table 8:
Table 9:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 3:
Table 4:
PNX15xx/952x Series
External Clocks
Bypass Clock Sources
Advantages of Centralized Clock Gating
Control
Registers Summar
CLOCK MODULE REGISTERS
Binary Sequence for the Common Boot Script
211
Flash TIming Parameters Used by the Default
Boot Scripts
Binary Sequence for the Section of the Flash
Boot
Host Configuration Sequence
Examples of I2C EEPROM Devices
PCI-XIO Register Summary
PCI Configuration Register Summary
Registers Description
PCI Configuration Registers
Timestamp Unit Registers
GPIO Time Counter
GPIO TM3260 Timer Input Select
GPIO Interrupt Status
Clock Out Select
GPIO Interrupt Registers for the FIFO Queues
(One for each FIFO Queue)
GPIO Module Status Register for all 12
Timestamp Units
GPIO POWERDOWN
GPIO Module ID
GPIO IO_SEL Selection Values
32-Byte Interleaving, 512 Columns
Mapping scheme: 1024-Byte Interleaving, 256
214
167
Connected Media Processor
213
. . . . . . . . . . . . . . . . . . . . . . . 162
304
. . . . . . . . . . . . . . . . . . . . . . 302
. . . . . . . . . . . . . . . . . . . . . . 309
. . . . . . . . . . . . . . . . . . . . 181
. . . . . . . . . . . . . . . . . . . 300
. . . . . . . . . . . . . . . . . . 242
. . . . . . . . . . . . . . . . . . 301
. . . . . . . . . . . . . . . . . 164
. . . . . . . . . . . . . . . . . 309
© NXP B.V. 2007. All rights reserved.
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303
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