HD64F2168VTE33 Renesas Electronics America, HD64F2168VTE33 Datasheet - Page 143

• Manufacturer Part Number: HD64F2168VTE33
• Manufacturer: Renesas Electronics America

Specifications of HD64F2168VTE33

• Cpu Family: H8S
• Device Core Size: 16/32Bit
• Frequency (max): 33MHz
• Interface Type: I2C/IrDA/SCI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 40KB
• # I/os (max): 106
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of
access states of the external address space. The BSC also has a bus arbitration function, and
controls the operation of the internal bus masters – CPU and data transfer controller (DTC).
6.1
• Extended modes
• Extended area division
• Address pin reduction
• Control address hold signal and aria select signal polarity
BSCS200A_000220030700
Two modes for external extension
Normal extended mode: Normal extension (when the ADMXE bit in SYSCR2 is 0)
Address-data multiplex extended mode: Multiplex extension (when the ADMXE bit in
Possible in normal extended mode
The external address space can be accessed as basic extended areas.
A 256-kbyte extended area can be set and controlled independently of basic extended areas.
A CP extended area can be set and controlled independently of basic extended areas.
In normal extended mode:
A 256-kbyte extended area from H'F80000 to H'FBFFFF can be selected using 18 address pins
and the CS256 signal.
A CP extended area (8 kbytes, basic mode) from H'FFC000 to H'FFDFFF can be selected
using 13 address pins and the CPCS1 signal.
A 2-kbyte area from H'FFF000 to H'FFF7FF can be selected using six to eleven address pins
and the IOS signal.
In address-data multiplex extended mode:
The external address space can be accessed as the following three extended areas.
H'F80000 to H'F8FFFF
H'FFC000 to H'FFDFFF
H'FFF000 to H'FFF7FF
These areas can be selected using 8 pins or 16 pins, which is a total of address pins and data
input/output pins.
The output polarity of IOS, CS256, CPCS1, and AH can be inverted by the PNCCS and
PNCAH bits in LPWRCR
Features
Section 6 Bus Controller (BSC)
64 kbytes
8 kbytes
2 kbytes
SYSCR2 is 1)
256-kbyte extended area
CP extended area
IOS extended area
Rev. 3.00, 03/04, page 101 of 830